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Ottawa, Ontario, Canada
Hybrid
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role can be performed Hybrid with three days per week onsite at our Ottawa office.
Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.
Meet the Team
We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design.
Your Impact
* You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer
* You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause
* You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script
* In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design methodology from conception to production.
* You will collaborate with cross-functional teams from Testing, ATE, reliability, packaging, and hardware design team
Minimum qualifications:
* BSEE degree with 8+ years of experience or equivalent or an MS degree with 6+ years of experience, or equivalent or a PhD with 3+ years of experience, or equivalent
* Design, simulation and measurement of high speed ICs experience in at least 3 areas below:
High Speed Serial Links utilizing serializers, deserializers, and data convertors, voltage regulators, output drivers, phase locked loops, clock transmission/propagation, opamps, programmable gain amplifiers, and equalization
Preferred qualifications:
* Experience with electrical transceiver applications including backplane and cable communications
* Experience with FinFET technology
* High-frequency layout experience a plus: Passive component design: inductors,
* transformers, transmission-lines, etc.
* Floorplanning (power/ground, digital/analog signal routing, etc.) experience
* Custom transistor layout experience
* Experience designing for manufacturability
* Experience with ESD laboratory practices and methodology
* Experience with Cadence (virtuoso), Spectre/APS/SpectreX, Matlab, EMX
* Experience with mixed-signal simulations in AMS
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Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$168,800.00 - $277,400.00Non-Metro New York state & Washington state:
$148,800.00 - $248,200.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.