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Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.
Job Description
Position Responsibilities:
Design and implement video compression, image processing, vector processing, neural network accelerators, processor cores, and memory subsystems using Verilog and SystemVerilog.
Perform logic design, implementation, and verification utilizing Verilog, SystemVerilog, and relevant programming and scripting languages.
Synthesize and optimize RTL for performance, area, and power efficiency.
Develop and enhance front-end design methodologies and tool flows.
Contribute to chip bring-up and validation efforts.
Analyze code and functional coverage metrics, and collaborate with the verification team to identify and address coverage gaps.
Qualifications:
Master’s degree in Electrical, Electronics, or Computer Engineering, with 0–5 years of relevant experience.
Solid understanding of computer architecture, logic design, and VLSI design principles.
Proficiency in SystemVerilog, Verilog, and Perl. Familiarity with design verification methodologies and functional coverage concepts.
Experience with scripting languages and the ability to write assembly language programs.
Strong communication skills and a collaborative, team-oriented mindset.
Demonstrated problem-solving skills and analytical thinking.
Knowledge of logic synthesis and timing closure is a plus.
