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Barcelona, Spain, Spain
Hybrid
Join the Physical Design CAD & Methodology Team—a technically strong group responsible for developing and supporting RTL-to-GDS Physical Design implementation and signoff flows across multiple ASIC programs.
Our team works closely with Physical Design, STA, Power, Physical Verification, and Front-End teams to enable efficient execution, consistent QoR, and reliable tape-outs. We value engineers who combine hands-on technical depth with a growing sense of ownership, collaboration, and continuous improvement. If you enjoy improving flows, solving complex PD problems, and expanding your technical influence, this role is a great fit.
As a Physical Design Flow & Methodology Engineer, you will take end-to-end ownership of key portions of the PD flow, contributing to implementation and signoff methodology from synthesis handoff through GDS delivery.
You will develop, enhance, and maintain block- and chip-level PD flows, debug timing, power, congestion, and physical verification issues, and work closely with design teams to improve convergence and predictability. You will contribute to methodology definition, automation, and best practices, and help drive adoption across projects.
In this role, you will wok on implementation tool flows and methodologiesto enhance and add new features. Your work will have direct impact on QoR, turnaround time, and tape-out success, while allowing you to grow toward senior-level technical leadership.
Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in ASIC Physical Design, PD flow/methodology, or CAD engineering
Hands-on experience with Physical Design implementation and tools, such as: Fusion Compiler or Innovus, PrimeTime or Tempus
Strong understanding of RTL-to-GDS Physical Design flow, including synthesis handoff, placement, CTS, routing, and ECOs
Solid experience with timing, power, and physical verification signoff
Proficiency in at least one scripting language (Tcl, Python, or Shell)
Ability to independently debug flow, tool, and QoR issues and propose improvements
Experience contributing to PD flow automation and methodology enhancements
Familiarity with ASIC signoff collateral, including: Liberty (.lib), LEF/DEF, GDS; SDC, SPEF, SDF
Multi-voltage design experience
Understanding of MCMM timing and signoff strategies
Exposure to power integrity analysis (IR drop, EM/EMIR)
Experience supporting or mentoring junior engineers
Strong attention to detail with a focus on quality, reproducibility, and maintainability
Ability to clearly document flows and communicate methodology updates to users
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
