Bengaluru, Karnataka, India
Onsite
Meet The Team:
Our creative and talented Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
Your Impact:
Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
Good understanding of different CTS strategies and providing the feedback to Implementation Team.
As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work.
STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.
Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Good scripting skills (TCL/SHELL/PERL/Python) is a MUST
Minimum Qualification:
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
You are an ASIC engineer with 13+ years of related work experience with a broad mix of technologies including:
All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
Hierarchical design implementation approach, Timing closure, physical convergence.
Power Integrity Analysis
Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies.
Preffered Qualifications:
Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2
Synthesis Tools: Synopsys DC/FC
Formal Verification : Synopsys Formality and Cadence LEC
Static Timing verification: Primetime-DMSA
Power Integrity : Apache Redhawk
Physical Design Verification Synopsys ICV, Mentor Calibre
Scripting: TCL, Perl is required; Python is a plus
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