Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Meet the Team
Join a dynamic Design Verification team responsible for delivering robust wireless modem IP and SoC solutions across multiple product programs. We work closely with Architecture, RTL Design, DSP/Algorithm, Firmware, RF, and Post-Silicon Validation teams across global locations to ensure high-quality silicon delivery. Collaboration, innovation, technical excellence, and continuous improvement define our culture, making this an exciting opportunity to contribute, grow, and make a significant impact.
About the Role
We are seeking an experienced Modem Verification Engineer to join our Silicon Engineering team in Hyderabad. In this role, you will own verification of wireless modem IP, subsystems, and SoCs, with a focus on PHY/MAC functionality, modem datapaths and control, and digital/RF interfaces.
You will develop verification plans and reusable UVM environments, create coverage-driven tests and checkers, debug complex protocol and integration failures, and drive features from specification review through sign-off. You will also collaborate with cross-functional and global teams and improve verification methodology, automation, regression efficiency, and reusable infrastructure.
This is an excellent opportunity to solve challenging cross-layer verification problems and contribute directly to next-generation wireless connectivity products.
Responsibilities
- Develop and execute verification plans for wireless modem IP, subsystems, and SoCs, with clear feature, coverage, and sign-off criteria.
- Build, enhance, and maintain reusable SystemVerilog/UVM verification environments, including agents, sequences, scoreboards, assertions, and coverage models.
- Create directed and constrained-random tests and drive functional and code coverage closure through systematic gap analysis.
- Verify modem datapaths and control functions, PHY/MAC interactions, digital/RF interfaces, registers, buses, memories, clocks, resets, and interrupts.
- Run and debug RTL and gate-level regressions and perform root-cause analysis of protocol, timing, and subsystem/SoC integration failures.
- Collaborate with Architecture, RTL Design, DSP/Algorithm, Firmware, RF, and Post-Silicon Validation teams across global sites.
- Own assigned features from specification review through verification closure and sign-off, with proactive communication of status, risks, and dependencies.
- Improve verification productivity through scripting, regression automation, continuous integration, reusable infrastructure, and metrics-driven debug.
- Participate in architecture, design, test-plan, and coverage reviews and provide clear technical feedback early in the development cycle.
- Analyze regression and coverage metrics, identify issues early, and drive failures to closure with the appropriate cross-functional owners.
- Contribute to team knowledge sharing, verification best practices, and mentoring of junior engineers.
Requirements
- B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related field.
- Typically 5–8 years of hands-on ASIC/SoC Design Verification experience; candidates with greater experience and strong role alignment will also be considered.
- Strong expertise in SystemVerilog, UVM, constrained-random verification, SystemVerilog Assertions (SVA), functional coverage, and regression management.
- Experience verifying wireless modem or connectivity IP at block, subsystem, or SoC level.
- Good understanding of PHY/MAC architecture, digital design fundamentals, SoC architecture, and digital/RF integration.
- Strong debug skills using tools such as Verdi, DVE, or SimVision and simulators such as VCS, Xcelium, or Questa.
- Proficiency in C/C++ and scripting with Python, Tcl, or Shell for test development, modeling, and automation.
- Ability to work independently, solve complex cross-layer issues, and communicate effectively with cross-functional and geographically distributed teams.
Preferred Qualifications
- Experience with Wi-Fi and/or low-power wireless technologies such as BLE, Zigbee, Thread, or Matter.
- Knowledge of DSP and communication-system fundamentals and experience working with MATLAB, Simulink, or algorithm reference models.
- Experience with gate-level simulation, SDF timing debug, CDC/RDC analysis, or low-power verification methodologies such as UPF.
- Experience with formal verification, emulation, FPGA prototyping, performance verification, or hardware-software co-verification.
- Experience with Git-based development, Jenkins or other CI workflows, scalable regression infrastructure, and data-driven verification automation.
Benefits & Perks:
Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
- Equity Rewards (RSUs)
- Insurance plans with Outpatient cover
- National Pension Scheme (NPS)
- Flexible work policy
- Childcare support
Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.
