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San Jose, California, United States, United States of America
Onsite
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera’s most advanced FPGA, SoC, and multi-die silicon platforms. This role sits at the forefront of innovation in high-performance compute, AI acceleration, advanced packaging, and heterogeneous integration.
You will own the end-to-end DFT strategy for complex, large-scale silicon programs and influence technical direction across multiple product generations. You will architect scalable, robust, and forward-looking DFT solutions spanning scan, compression, MBIST/LBIST, hierarchical DFT, IJTAG/IEEE standards, silicon debug, and production test optimization. You will partner deeply with architecture, RTL, physical design, validation, product engineering, and manufacturing teams to ensure world-class testability, manufacturability, and silicon quality.
This role requires exceptional depth in modern DFT methodologies, strong architectural vision, and the ability to drive alignment across broad engineering organizations. You will mentor teams, shape methodology roadmaps, and represent DFT as a key decision-maker in silicon architecture and execution.
Key Responsibilities:
DFT Strategy Ownership: Define and drive the long-term DFT architecture for FPGA, SoC, processor, DSP, SERDES, IO, and multi-die/chiplet-based products.
Methodology Leadership: Lead development of scalable DFT methodologies and flows across RTL, gate-level, hierarchical, and multi-die integration environments.
Advanced DFT Architecture: Architect state-of-the-art scan, compression, ATPG, MBIST, LBIST, boundary scan, and in-system test solutions to meet aggressive coverage, quality, and cost goals.
Multi-Die & Advanced Packaging DFT: Drive DFT planning and integration for 2.5D/3D ICs, chiplets, and heterogeneous multi-die systems.
Cross-Functional Integration: Collaborate with architecture, RTL, PD, STA, validation, and product engineering teams to ensure seamless DFT integration throughout the design lifecycle.
DFT Governance: Establish and enforce DFT guidelines, test specifications, timing constraints, and signoff criteria across large engineering programs.
Silicon Debug Leadership: Lead root-cause analysis for pre-silicon and post-silicon test failures, yield issues, and manufacturing escapes.
Manufacturing Test Optimization: Optimize production test strategies for coverage, test time, yield improvement, power-aware test, and overall efficiency.
Technology Innovation: Drive adoption of next-generation DFT technologies, automation, and best practices to improve productivity and scalability.
Technical Mentorship: Mentor DFT engineers and provide technical leadership across multiple programs.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $299,200 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Minimum Qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years of industry experience.
10+ years architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi-die designs.
10+ years experience in scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, and hierarchical DFT.
10+ years experience with RTL-to-GDS DFT integration including scan insertion, STA constraints, low-power DFT, and gate-level verification.
10+ years experience with industry-standard EDA tools for synthesis, scan insertion, ATPG, simulation/debug, formal verification, and STA.
10+ years experience supporting silicon bring-up, manufacturing test flows, yield analysis, and failure debug.
10+ years experience developing DFT automation using scripting languages (Perl, Python, TCL).
10+ years experience providing technical leadership and driving cross-functional alignment.
Preferred Qualifications:
Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Experience with advanced fault models, diagnosis, and silicon analytics.
Experience with 2.5D/3D ICs, chiplet architectures, and high-speed IO/SerDes DFT.
· Familiarity with IEEE DFT standards including IJTAG (1687), JTAG (1149.x), and embedded instrumentation.
Experience with power-aware DFT, low-power ATPG, and large-scale test optimization.
Experience with developing highly efficient & scalable DFT methodology & flows that incorporates AI technologies.
Experience mentoring teams and influencing DFT strategy across multiple product families.