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Sydney, New South Wales, Australia
Onsite
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role
We are looking for talented engineers across multiple experience levels to ensure the highest quality of our CPU IP. Whether you are an emerging engineer looking to grow your skills or an industry veteran ready to architect complex verification environments, you will play a crucial role in our ASIC design cycle.
The exact scope of your responsibilities, technical ownership, and leveling will be tailored to your experience and demonstrated capabilities.
Key Responsibilities
Develop, maintain, and enhance block-level and sub-system testbenches using System Verilog and UVM.
Extract verification requirements from architecture specifications and participate in test plan reviews.
Write directed and constrained-random tests to achieve high functional and code coverage metrics.
Debug simulation failures and collaborate closely with RTL designers to resolve complex issues.
Maintain and optimize automated regression setups.
Mandatory Requirements
1+ years of experience with a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Strong foundational grasp of advanced computer architecture (pipelines, memory hierarchies, caches).
Knowledge in System Verilog (SV) and the Universal Verification Methodology (UVM).
Deep understanding of hardware verification concepts, including constrained-random stimulus generation and coverage-driven verification.
Familiarity with scripting languages (e.g., Python, Perl, Bash) to automate workflows.
Preferred Qualifications
Working knowledge of Reliability, Availability, and Serviceability (RAS) architecture.
Proven experience or familiarity with RAS verification techniques, including error correction code (ECC) testing, parity generation/checking, data poisoning, and hardware fault injection.
Comprehensive knowledge of the RISC-V Instruction Set Architecture (ISA) and custom extensions.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.