# **We're Building the Next Generation of Chips to Power AI. Join Us.**
**At Zetta, we're building the next NVIDIA to accelerate AI discovery. Our XPU chips are state-of-the-art AI compute engines**, versatile and efficient enough to support **_AGI_**, and eventually **_ASI_**, without requiring massive power infrastructure.
The team consists of exceptional engineers **obsessed** with pushing the boundaries of what's possible in computing, **and we're now seeking our next technical member!**
### **You Are**
* **Ready to go all-in and do the work of your life**
* **Willing to be hardcore when pushing technical boundaries**
* A systems-level hardware engineer who thinks from chip pins all the way to the data center floor
* Deeply **passionate** and **obsessed** with computing and AI
* Hungry to build something that actually matters
### **Your Background**
* Background in Electrical Engineering, Mechanical Engineering, Engineering Physics, _or equivalent field_
* **Strong high-speed PCB design experience** (high layer count, controlled impedance, stackup design, via optimization)
* **Signal integrity & power integrity expertise** (SI/PI simulation, eye diagrams, S-parameter analysis, decoupling strategy, IR drop)
* **High-speed interface design** (PCIe Gen5/6, CXL, DDR5/HBM, Ethernet 400G/800G, SerDes routing)
* **Proficiency with PCB toolchains** (Altium, Cadence Allegro, KiCad, HyperLynx, Ansys SIwave/HFSS)
* **Cluster & system-level design experience** (server/blade architecture, backplanes, rack-scale interconnect topologies)
* **Thermal & cooling expertise** (air, liquid, and immersion cooling; thermal simulation; cold plate design; airflow modeling)
* **Power delivery design** (multi-phase VRMs, high-current PDN, board-level power sequencing)
* **Bring-up & debug expertise** (oscilloscopes, VNAs, TDR, BERT, JTAG, root-causing SI/PI/thermal issues on real boards)
* **Build/flow automation and tooling** (Python, Tcl, Nix)
* **Work across PCB, mechanical, thermal, and system architecture** to hit cluster-level PPA targets
### **Huge Plus If**
* **Experience designing AI/HPC accelerator boards or systems** (GPU servers, TPU pods, custom ASIC carrier boards)
* **Rack-scale & data center experience** (OCP designs, NVLink/NVSwitch-class fabrics, optical interconnects, top-of-rack networking)
* **DFM/DFT-aware PCB design** (manufacturability reviews, test point strategy, boundary scan, bed-of-nails)
* **1+ years (or equivalent) designing high-speed, high-layer-count PCBs** for ASICs, GPUs, or networking gear
* **Mechanical/enclosure design experience** (sheet metal, chassis design, working with ME/Industrial Design teams)
* **HW/SW boundary experience** (board bring-up, BMC/firmware, telemetry, profiling, build systems)
* Autodidactic polymath with a strong mathematical background
* **Someone who doesn't fret when faced with near-impossible technical challenges**
### **The Opportunity**
* **Be one of the first employees shaping a revolutionary technology**
* Work directly with the founding team of exceptional engineers at our San Francisco HQ
* Own critical decisions that will influence the future of AI compute
* Grow into a technical leader as we scale
* Highly competitive compensation + significant equity
**This is THE chance to do the work of your life.** The chance to build something that will be remembered. **To go hardcore on a technical moonshot that will actually matter for over 100 to 1,000 years.**
Visa sponsorship is offered for this role.
