Partcl is ending the [hardware lottery](https://arxiv.org/abs/2009.06489).
We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools.
We are looking for extremely talented engineers who understand machine learning and systems at a deep level: engineers who can jump between performant architectures and CUDA kernels with ease, optimize inference pipelines, and develop systems that can grok terabytes of data in seconds.
At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us.
**What you will do:**
* Explore new ML model architectures which give 1000x performance over existing methods for chip design.
* Architect and build end‑to‑end pipelines: high‑performance kernels, efficient file IO, training models, latency sensitive inference, CLI/UI layers.
* Talk to customers, deploy in their office, fix prod on the fly.
* Learn quickly.
**Requirements:**
* Expert in PyTorch and CUDA programming.
* Deep understanding of systems - memory, latency, and performance tradeoffs.
* Experience designing, training and deploying custom models (a GPT wrapper does not count).
* Versatility: comfortable toggling between model architecture design, low‑level optimization and scaleable system design (N\~>10M).
* Proficient with GPU profiling and performance analysis.
**Nice to Have:**
* Exposure to chip design and electronic design automation (EDA).
* Expert in Reinforcement Learning
* Research in compilers, programming languages.
* Papers in respected conferences and journals.
* Experience with physics-driven ML.
Visa sponsorship is offered for this role.
