FPGA Design Engineer

FPGA Design Engineer

The Opportunity:

We are seeking an experienced FPGA Design Engineer to support the development, optimization, and deployment of digital signal processing (DSP) functions on FPGA platforms. As a member of our engineering team, you will be responsible for designing, implementing, and validating high-performance digital systems that efficiently translate complex algorithms into synthesizable hardware for RF applications. This role involves contributing to advanced DSP workflows, enhancing real-time processing capabilities, and advancing our algorithm-to-hardware development pipeline. You will work both independently and collaboratively with multidisciplinary teams, leveraging your technical expertise to address complex challenges with minimal supervision and providing mentorship as appropriate.

Our research and development environment prioritizes innovation, rapid prototyping, and problem-solving through direct hands‑on application of concepts. This position offers the opportunity to engage directly with FPGA and RF technologies and deliver impactful operational solutions. We invite you to join us in advancing our FPGA-enabled DSP and RF processing solutions.

What You'll Do:

• Design and implement FPGA‑based DSP systems using, HDL, Vitis HLS and modern FPGA toolchains

• Develop, optimize, implement DSP algorithms, including filtering, detection, synchronization, modulation and demodulation, transforms, and feature‑extraction into high‑throughput, resource‑efficient hardware blocks.

• Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures

• Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints

• Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows

• Develop reusable hardware IP blocks, enabling scalable DSP pipelines and accelerating future development

• Maintain documentation, including design notes, block diagrams, interface definitions, user guides, and workflow references

• Contribute to innovation, identifying new techniques and technologies that improve FPGA development efficiency, DSP performance, or overall system capability

Join us. The world can't wait.

You Have:

• 3+ years of experience developing FPGA or SDR solutions for DSP or RF applications, including prototyping DSP algorithms in hardware such as filtering, detection, synchronization, modulation, demodulation, transforms, and feature extraction

• Experience designing FPGA solutions using Verilog, VHDL, SystemVerilog, or HLS and working with Xilinx, Vitis, or Vivado development ecosystems

• Experience applying FPGA toolchain workflows, including simulation, synthesis, fitting, timing analysis, implementation, and hardware debug

• Experience integrating FPGA designs with embedded hardware systems or FPGA‑connected RF front ends and adapting vendor RF transceiver reference designs, such as RTL, IP cores, or drivers, to evaluation boards or custom platforms

• Experience using Python, C++, or MATLAB for modeling DSP algorithms, as well as scripting with Python, Bash, or Tcl for automation workflows

• Knowledge of embedded systems concepts, including memory interfaces, buses, soft‑core CPUs, and high‑speed digital interfaces such as AXI‑Stream, AXI‑Lite, DMA, and custom streaming buses

• Knowledge of Linux or UNIX development environments and digital design fundamentals, including streaming architectures, pipelining, buffering, and DataPath timing

• Ability to read hardware schematics, operate lab equipment including logic analyzers, oscilloscopes, and spectrum analyzers, and collaborate in multidisciplinary teams while also working independently on complex engineering tasks

• Ability to obtain a Secret clearance

• Bachelor’s degree

Nice If You Have:

• Experience building DSP IP libraries for reuse across modem or signal‑processing applications

• Experience with SystemVerilog or UVM for verification

• Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation

• Experience with C/C++ or Rust for embedded or performance‑critical firmware

• Experience with GPU acceleration, parallel computing, or high‑bandwidth data processing

• Experience gathering requirements, shaping development roadmaps, or supporting Agile workflows

• Knowledge of modern agentic engineering workflows, such as AI‑driven automation for FPGA design, simulation, synthesis, or testing

• Master's degree in Electrical Engineering, Computer Engineering, or related field

Clearance:

Applicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information.

Compensation

At Booz Allen, we celebrate your contributions, provide you with opportunities and choices, and support your total well-being. Our offerings include health, life, disability, financial, and retirement benefits, as well as paid leave, professional development, tuition assistance, work-life programs, and dependent care. Our recognition awards program acknowledges employees for exceptional performance and superior demonstration of our values. Full-time and part-time employees working at least 20 hours a week on a regular basis are eligible to participate in Booz Allen’s benefit programs. Individuals that do not meet the threshold are only eligible for select offerings, not inclusive of health benefits. We encourage you to learn more about our total benefits by visiting the Resource page on our Careers site and reviewing Our Employee Benefits page.

Salary at Booz Allen is determined by various factors, including but not limited to location, the individual’s particular combination of education, knowledge, skills, competencies, and experience, as well as contract-specific affordability and organizational requirements. The projected compensation range for this position is $69,400.00 to $158,000.00 (annualized USD). The estimate displayed represents the typical salary range for this position and is just one component of Booz Allen’s total compensation package for employees. This posting will close within 90 days from the Posting Date.

Identity Statement

As part of the hiring process, we will ask you to complete an identity verification process that leverages advanced biometrics and artificial intelligence to ensure authenticity and protect against identity fraud. You are expected to be on camera during interviews and assessments. We reserve the right to take your picture to verify your identity and prevent fraud.

Candidate AI Usage Policy

AI is a part of our daily work at Booz Allen, and we are committed to the responsible and ethical use of AI tools. However, we want to ensure a fair candidate process based on your own skills and knowledge. As part of this commitment, the use of artificial intelligence (AI) or other tools to assist with responses during interviews (whether in-person or virtual) is prohibited unless permission is explicitly provided.

Work Model
Our people-first culture prioritizes the benefits of collaboration, whether it occurs in person or virtually. To support engagement and effective communication, employees working virtually are generally expected to have their cameras on during meetings.

• Remote: If this position is listed as remote, there may still be occasions when you are required to work in person at a Booz Allen or customer facility.

• Hybrid: If this position is listed as hybrid, you will be expected to work from a Booz Allen facility frequently, in alignment with leadership expectations and the needs of the role. You may also be required to work from or visit a customer facility.

• Onsite: If this position is listed as onsite, work will primarily be performed at a Booz Allen office or customer facility, where employees will collaborate directly with colleagues and customers as required by the role.

Commitment to Non-Discrimination

All qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local, or international law.