FPGA Engineer - Chip Design

Accountabilities:

Develop realistic engineering evaluation tasks spanning RTL design, functional verification, logic synthesis, physical design, and sign-off.
Create high-quality reference implementations using Verilog, SystemVerilog, or VHDL, supported by testbenches, design constraints, expected outputs, and validation procedures.
Establish clear grading criteria and assessment methodologies that reflect industry-standard chip-design practices and engineering expectations.
Evaluate AI-generated RTL code, testbenches, hardware designs, and implementation results to identify functional errors, architectural weaknesses, and design inefficiencies.
Diagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area (PPA) trade-offs.
Assess hardware designs based on functional correctness, timing requirements, resource utilization, implementation quality, and overall design robustness.
Configure, maintain, and improve electronic design automation (EDA) environments that enable AI agents to execute realistic chip-design workflows.
Apply relevant industry tools and workflows, including Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, and Intel Quartus, depending on the evaluation requirements.
Design evaluation scenarios covering synthesis quality, place-and-route outcomes, static timing analysis, timing constraints, and timing closure.
Identify recurring failure patterns in AI-generated designs and translate them into new test cases, evaluation scenarios, and more challenging engineering benchmarks.
Collaborate with engineering and research teams to improve evaluation frameworks, testing strategies, technical benchmarks, and overall assessment quality.
Automate design workflows, testing procedures, and results analysis using scripting languages such as Python, Tcl, or Perl.
Document reference designs, engineering assumptions, known failure cases, evaluation criteria, and methodologies to ensure reproducibility and consistency.
Requirements:
Have at least 3 years of relevant professional experience, with approximately 3–5 years of hands-on ASIC or FPGA design experience preferred, ideally covering multiple stages of the digital design lifecycle.
Hold a B.E., B.Tech, or M.Tech degree in Electrical Engineering, Electronics Engineering, VLSI, or a related technical discipline.
Demonstrate strong RTL development skills in Verilog, SystemVerilog, or VHDL, with the ability to develop reliable, maintainable, and functionally correct hardware designs.
Have practical experience in digital design verification, including testbench development, debugging, coverage analysis, and methodologies such as UVM or equivalent verification approaches.
Possess working knowledge of industry-standard EDA tools and workflows, including platforms from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel.
Understand logic synthesis, physical design, place-and-route, static timing analysis, timing constraints, and timing closure.
Demonstrate sound engineering judgment when evaluating PPA trade-offs, implementation quality, resource utilization, and design feasibility.
Have experience taking at least one chip-design project from specifications through implementation or tape-out, with a solid understanding of the associated engineering challenges.
Possess strong analytical, debugging, and problem-solving skills, including the ability to identify root causes and clearly explain why a design succeeds or fails.
Be capable of developing structured technical assessments, defining objective evaluation criteria, and documenting findings with precision.
Have familiarity with Python, Tcl, or Perl for scripting, workflow automation, and engineering data analysis; experience with these tools is an advantage.
Have exposure to open-source hardware design and verification tools such as Yosys, OpenROAD, Verilator, or cocotb, which is beneficial.
Demonstrate an interest in AI engineering evaluations, reinforcement-learning environments, or model post-training; previous experience in these areas is a plus but not mandatory.
Be comfortable working independently in a remote environment while collaborating effectively with multidisciplinary engineering and research teams.
Benefits:
Competitive salary: INR 12,00,000–20,00,000 per year (12–20 LPA), depending on experience and qualifications.
Fully remote work: Work remotely from India, offering flexibility without a required office-based arrangement.
Full-time opportunity: A full-time position focused on advanced semiconductor engineering and AI-driven chip-design evaluation.
Cutting-edge technical exposure: Apply ASIC and FPGA design expertise to emerging AI systems, engineering evaluations, and automated hardware-design workflows.
End-to-end design experience: Work across RTL development, verification, synthesis, physical implementation, and timing analysis.
Research and engineering collaboration: Partner with technical teams to improve AI evaluation methodologies, design benchmarks, and testing environments.
Professional growth: Strengthen expertise in hardware design, verification, EDA workflows, automation, and PPA optimization.
Additional benefits: Specific details regarding healthcare coverage, paid leave, bonuses, equipment allowances, and other employment perks have not been provided and should be confirmed during the hiring process.