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San Jose, California, United States
Onsite
Working COMPANY OVERVIEW
The Future of Intellectual Property is Here
Electronic innovation is everywhere, from smart sensors to smart cities, and it is transforming the way people work, live, and play. Cadence is excited to play a role in this innovation, not only as a world leader in electronic design automation (EDA) for over 25 years, but also as a driving force in the advancement of intellectual property (IP).
Cadence® IP solutions will change the way you think about and use IP in your system-on-chip (SoC) designs. As you use more IP to fortify your SoCs with new functionalities, we can help you reduce the complexity and risk inherent in designing for smart technology while meeting your performance, area, and power (PPA) requirements.
Cadence is the fastest-growing silicon IP provider, with a proven portfolio and many industry firsts in design IP and verification IP. Engineers choose Cadence when they want the best in interface, memory, analog, peripherals, processor, and verification IP.
Our Goal: a Perfect Fit in Your SoC
Cadence provides an open IP platform and IP Factory approach so you can design, customize, and verify IP and IP subsystems to fit your SoCs in ways that weren’t possible before. We work with you to make sure our IP fits as seamlessly as possible into your designs. Growing synergies within our IP portfolio, and between our IP portfolio and EDA tools, provide you with important flexibility and time-to-market advantages over traditional IP integration approaches.
Quality is Integral to What We Do, Not an Afterthought
Cadence has amassed thousands of IP tape outs, and our IP solutions are in use by many of the world’s leading semiconductor and systems companies. The Cadence quality assurance program is based on clear, documented policies and reproducible procedures that begin in product definition and development and extend through testing and release to ongoing maintenance and support. Our procedures include specification and maintenance of appropriately detailed product definitions and test/release plans for every Cadence product.
POSITION DETAILS
High Speed SERDES PHY Firmware Design Engineer (T1/T2)
This is an opportunity to join a dynamic and growing team of experienced engineers developing physical IP for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who is able to work independently to complete assigned tasks and can also contribute to project leadership. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES from architecture development to implementation, verification, testing and customer deployment.
This includes:
Responsibilities include:
Specific desired skills:
The annual salary range for California is $101,500 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.