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Bengaluru, Karnataka, India
Onsite
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Block Level and Full chip level Static(IR)/Dynamic(IVD) sign-off
Power Estimation on blocks and full chip (both vector and vectorless)
Signal/Power EM sign-off at Block level and Full chip
Custom power grid implementation for block/hardmacs
System level Analysis (PDN) with board, package, interposer and die
Work with SoC and packaging team in bump assignment, pkg routing optimization
Dynamic analysis with vectorless/vectors/mixed mode analysis
PG Grid resistance checks
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