Machine Learning for Physical Design Intern - CPU/AI Hardware

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.