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San Jose, California, United States
Onsite
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
Altera is seeking an accomplished Memory Validation Architect to define and lead the validation architecture for next-generation memory subsystems across our FPGA portfolio. This is a highly visible technical leadership role responsible for shaping the validation strategy for DDR5, LPDDR5/LPDDR6, HBM, and future memory technologies from architecture definition through production.
The ideal candidate is a recognized industry expert with deep experience in memory controller and PHY architectures, post-silicon validation, system architecture, silicon debug, and customer enablement. You will partner closely with architecture, RTL, firmware, board design, signal integrity, software, product engineering, and key memory vendors to ensure industry-leading quality, performance, interoperability, and customer success.
Beyond execution, you will define scalable validation methodologies, influence product architecture, mentor engineering teams, and establish best practices that span multiple FPGA generations.
Define and own the end-to-end validation architecture and strategy for memory subsystems across multiple FPGA product families.
Drive validation planning from architecture definition through silicon bring-up, product qualification, and customer deployment.
Architect scalable validation frameworks, reusable infrastructure, and automation capable of supporting multiple product generations.
Lead pre-silicon and post-silicon validation strategy for:
DDR5, LPDDR5 and HBM
Memory controllers
PHYs
Training and calibration algorithms
Define comprehensive validation methodologies covering:
Functional correctness
Performance characterization
Margining
Reliability
Stress testing
Error injection and recovery
Compliance and interoperability
Establish silicon characterization methodologies including voltage, temperature, frequency, process variation, and manufacturing margin analysis.
Lead complex root-cause investigations involving RTL, firmware, board design, signal integrity, package interactions, and system software.
Drive architecture improvements by identifying validation gaps and influencing future memory subsystem designs.
Partner with board design and signal integrity teams to optimize channel topology, routing, stack-up, termination, power delivery, and overall memory subsystem robustness.
Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early technology enablement.
Define customer validation strategies and drive rapid resolution of customer-reported issues.
Establish metrics and dashboards that measure validation coverage, product quality, debug efficiency, and execution readiness.
Champion AI-driven validation, automation, analytics, and intelligent debug methodologies to improve engineering productivity.
Mentor senior engineers and provide technical leadership across the memory validation organization.
Strategic technical leadership with the ability to influence product direction.
Exceptional debugging and analytical skills for solving complex silicon and system-level problems.
A passion for building scalable validation methodologies and world-class engineering practices.
Strong communication skills with the ability to collaborate effectively across executive leadership, engineering teams, customers, and industry partners.
A customer-first mindset focused on delivering industry-leading product quality, reliability, and performance.
This role offers a unique opportunity to define the future of memory validation for industry-leading FPGA products. As a Memory Validation Architect, you will influence product architecture, shape validation strategy across multiple generations, mentor engineering teams, and play a critical role in delivering innovative programmable solutions to customers worldwide.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $303,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 15+ years of industry experience in memory subsystem architecture, silicon validation, high-speed interface development, or a related field; OR Master's degree with 13+ years of related industry experience; OR Ph.D. with 10+ years of related industry experience.
10+ years of hands-on experience designing, validating, debugging, or optimizing DDR memory technologies, including DDR4, DDR5, LPDDR4, LPDDR5, HBM, or newer JEDEC-compliant memory standards.
10+ years of experience with at least four of the following: Memory controller architecture or DDR PHY architecture or Memory initialization and training or DDR calibration algorithms or JEDEC memory specifications or Memory timing analysis and scheduling
8+ years of experience leading or contributing to silicon bring-up, silicon debug, characterization, validation, and production qualification for complex SoCs or memory subsystems.
8+ years of experience performing board-level signal integrity (SI), power integrity (PI), timing analysis, or high-speed memory channel validation.
5+ years of hands-on experience using high-speed laboratory validation equipment such as oscilloscopes, protocol analyzers, logic analyzers, Bit Error Rate Testers (BERTs), traffic generators, or equivalent debugging tools.
5+ years of programming or automation experience using Python, C/C++, or similar scripting or programming languages to develop validation, debug, characterization, or test automation solutions.
5+ years of experience leading cross-functional technical projects involving at least three of the following disciplines: architecture, RTL design, firmware, silicon validation, software development, customer engineering, or product engineering.
Experience with FPGA or ASIC memory subsystem development.
Expertise in HBM, CXL Memory, Compute Express Link, or emerging memory technologies.
Experience working with major DRAM vendors including Micron, Samsung, and SK hynix.
Strong understanding of PCIe, CXL, AXI, AMBA, and coherent interconnect architectures.
Experience defining organization-wide validation methodologies and automation frameworks.
Demonstrated success influencing architecture decisions across multiple product generations.
Experience leading globally distributed engineering teams and mentoring senior technical contributors.