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San Jose, California, United States, United States of America
Onsite
Available
About Altera
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, communications, automotive, and edge computing. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of programmable logic.
About the Role
We are seeking a highly accomplished Physical Design Technical Lead who thrives at the intersection of disciplined engineering excellence and bold technical innovation. In this role you will own complex SOC and block-level implementation challenges end-to-end — from floorplan and power intent through final signoff — while actively shaping the evolution of our ML/AI-driven implementation flows. This is a high-visibility, high-impact position with a direct path to senior technical leadership.
Why This Role Stands Out
Best-in-class EDA toolchain: Synopsys Fusion Compiler, Cadence Innovus, industry-leading signoff suite
ML/AI-first flow strategy — you will help define it, not just use it
Tapeout cadence on leading-edge nodes
Collaborative, no-ego culture with world-class peers across design, DFT, and analog teams
Clear career ladder to Principal Engineer / Sr. Principal Engineer
Key Responsibilities:
SOC & Block-Level Implementation Leadership
Own floorplan architecture and power domain partitioning for large, multi-million instance SOC designs
Drive block-level implementation through synthesis, place-and-route, CTS, and ECO closure with sign-off quality results
Lead cross-functional convergence on timing, power, and area targets across multiple concurrent tapeout projects
Collaborate with RTL, DFT, packaging, and analog teams to resolve integration challenges proactively
Define and enforce physical design guidelines, constraint authoring (SDC/UPF), and methodology standards
Advanced Closure & Signoff
Achieve full signoff closure: STA (multi-corner multi-mode), IR drop, electromigration, DRC/LVS, antenna
Drive PPA optimization strategies including innovative floorplanning, clock topology, and routing resource planning
Lead critical-path analysis and timing-driven ECO resolution in partnership with design and library teams
Manage hierarchy and partitioning trade-offs for hierarchical vs. flat implementation flows
ML/AI Flow Innovation
Champion the integration of ML/AI-based optimization engines into production PnR flows
Hands-on experience with AI-assisted place-and-route, ML-based timing prediction, or reinforcement-learning PPA optimization
Evaluate and productize emerging AI tools from EDA vendors and internal research teams
Develop and maintain feedback loops between signoff results and ML training data pipelines
Partner with CAD and automation teams to deploy AI-driven ECO, congestion prediction, and closure acceleration scripts
Present findings and flow enhancements at internal design reviews and external EDA forums
Mentorship & Technical Leadership
Mentor and technically guide a team of 3–8 physical design engineers across multiple project tracks
Lead design reviews, closure reviews, and retrospectives; drive continuous improvement culture
Represent Physical Design in architecture planning meetings and influence design-for-implementability decisions
Contribute to internal white papers, methodology documentation, and IP reuse initiatives
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - 299,200 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Minimum Qualifications:
Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline with 15+ years of industry experience in physical design, physical implementation, or SoC backend design, including the following:
15+ years of progressive experience in physical design, physical implementation, or SoC backend development for advanced semiconductor products.
4+ years of experience in a technical lead, senior lead, or principal-level physical design role with ownership over complex physical design execution and delivery.
3+ successful tapeouts with direct hands-on physical design ownership at advanced process nodes, including 7nm or below.
5+ years of SoC-level floorplanning, top-level integration, and full-chip physical implementation experience, beyond block-level physical design ownership.
10+ years of hands-on experience with industry-standard physical design implementation tools such as Synopsys Fusion Compiler and/or Cadence Innovus.
8+ years of experience performing static timing analysis and timing closure using tools such as Synopsys PrimeTime, including MMMC analysis, SI/crosstalk closure, and path-based analysis.
5+ years of hands-on experience with power integrity analysis and signoff using tools such as Ansys RedHawk or Cadence Voltus for static and dynamic IR drop and electromigration (EM) analysis.
5+ years of experience implementing multi-voltage and low-power design methodologies using UPF and/or CPF, including MTCMOS, retention, isolation, and power intent implementation.
5+ years of experience with physical verification and signoff flows using tools such as Mentor Calibre DRC/LVS, with exposure to Cadence PVS and/or equivalent signoff tools.
8+ years of scripting and automation experience in physical design environments using Tcl, with 3+ years of experience using Python, Perl, or similar languages to improve design flow automation and engineering productivity.
2+ years of experience using or evaluating ML/AI-driven physical design tools or methodologies, such as Synopsys DSO.ai, Fusion Compiler AI, Cadence Cerebrus, or equivalent technologies.
2+ years of experience applying or supporting custom ML/AI-based physical design workflows for use cases such as timing prediction, hotspot detection, congestion modeling, or PPA optimization.
2+ years of experience interpreting ML model outputs, design metrics, or optimization recommendations and translating them into actionable physical implementation decisions.
2+ years of experience working with Python-based data pipelines, design metric collection, result analysis, or visualization workflows in support of physical design optimization.
Preferred Qualifications:
Experience with FPGA or structured-ASIC fabric implementation — Altera-specific knowledge is a distinct advantage
Exposure to 3DIC / chiplet integration: UCIe, EMIB, hybrid bonding physical design constraints
Prior work on high-speed I/O integration (PCIe Gen 5/6, HBM PHY, SerDes) within SOC physical implementation
Contributions to EDA vendor beta programs, academic publications, or conference presentations (DAC, ICCAD, SLIP)
Experience with formal verification handoff flows and CDC/RDC methodology integration
Familiarity with advanced signoff (path-delay rules, SI-aware fixing, advanced node design rule awareness)
Prior experience at semiconductor IP companies, EDA vendors, or top-tier fabless design houses