This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Principal CAD Engineer based in India.
This is a senior technical leadership opportunity focused on building and scaling advanced VLSI CAD methodologies and automation solutions.
You’ll help shape RTL-to-GDS implementation flows that improve design productivity, quality, runtime, and scalability across complex SoC programs.
The role spans synthesis, physical design, STA, low-power verification, physical verification, and signoff methodologies.
You’ll work closely with frontend, physical design, DFT, verification, and implementation teams, as well as EDA vendors and foundry partners.
The position combines deep technical ownership with flow architecture, automation, infrastructure development, and methodology leadership.
You’ll also mentor engineers and establish CAD best practices in a fast-moving, low-bureaucracy environment focused on delivering advanced silicon.
This is an opportunity to contribute to semiconductor infrastructure supporting demanding AI and high-performance computing applications.
Accountabilities:
- Architect, develop, deploy, and maintain scalable CAD flows covering synthesis, physical design, static timing analysis, low-power verification, physical verification, and signoff.
- Drive CAD methodology and automation improvements that increase design productivity, improve quality of results (QoR), reduce runtime, and enhance flow scalability.
- Partner with frontend, physical design, DFT, verification, and implementation teams to understand requirements and address flow deployment challenges.
- Debug complex CAD flow, EDA tool, infrastructure, and project-execution issues, identifying root causes and implementing robust solutions.
- Integrate, evaluate, and qualify new EDA tool releases, technologies, and methodologies for advanced semiconductor process nodes.
- Develop automation scripts, regression environments, dashboards, monitoring systems, and supporting infrastructure for reliable flow execution.
- Collaborate with EDA vendors and foundry partners on technology enablement, tool qualification, methodology development, and issue resolution.
- Establish and maintain CAD methodologies, documentation, standards, and best practices across engineering teams.
- Evaluate opportunities to improve distributed computing, workload management, and infrastructure utilization.
- Mentor CAD and engineering team members, provide technical guidance, and promote effective development and deployment practices.
- Contribute to successful tape-outs by ensuring CAD infrastructure and implementation methodologies are stable, scalable, and aligned with project requirements.
Requirements:
- Bachelor’s or Master’s degree in Electronics Engineering, Computer Engineering, VLSI, or a related technical discipline.
- 10+ years of professional experience in CAD engineering, physical design methodology, EDA flow development, or a closely related semiconductor engineering field.
- Strong expertise in ASIC/SoC implementation flows, including synthesis, place and route, STA, physical verification, and low-power methodologies.
- Hands-on experience with industry-standard EDA tool suites from vendors such as Cadence, Synopsys, and Siemens EDA.
- Strong programming and automation skills using Tcl, Python, Perl, and Shell scripting.
- Experience developing and maintaining regression frameworks and working with distributed computing environments and engineering infrastructure.
- Strong understanding of flow automation, methodology development, tool integration, and implementation challenges across complex SoC designs.
- Excellent debugging and analytical capabilities, with the ability to investigate complex technical problems and drive issues through resolution.
- Strong communication and stakeholder management skills, with the ability to work effectively across multidisciplinary engineering organizations.
- Demonstrated technical leadership and mentoring experience, with the ability to establish standards and influence engineering methodologies.
- Experience with cloud-enabled EDA infrastructure and workload management systems is a plus.
- Exposure to AI/ML-driven CAD optimization methodologies is desirable.
- Knowledge of advanced process nodes such as 5nm/3nm and multi-die or chiplet-oriented design flows is advantageous.
- A strong ownership mindset, bias for action, and ability to operate effectively in a fast-paced engineering environment.
Benefits:
- Fully remote work opportunity within India.
- Opportunity to work on advanced semiconductor and AI/HPC infrastructure technologies.
- High level of technical ownership and influence over CAD methodologies and engineering practices.
- Exposure to complex ASIC/SoC implementation challenges and advanced technology nodes.
- Collaboration with experienced engineering teams and external EDA and foundry partners.
- Opportunity to mentor engineers and shape scalable engineering standards and best practices.
- Fast-moving environment with limited bureaucracy and strong emphasis on technical excellence and execution.
- Opportunity to contribute to real silicon programs and high-impact semiconductor products.
- Professional growth through challenging technical projects spanning CAD, physical design, automation, and infrastructure.
How Jobgether works:
We use an AI-powered matching process to ensure your application is reviewed quickly, objectively, and fairly against the role's core requirements. Our system identifies the top-fitting candidates, and this shortlist is then shared directly with the hiring company. The final decision and next steps (interviews, assessments) are managed by their internal team.
We appreciate your interest and wish you the best!
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