Principal DSP SW Engineer

What you will do:

Lead the DSP software and firmware architecture for the 5G NR modem physical layer (PHY) for satellite non-terrestrial networks (NTN), define subsystem boundaries and interfaces, and guide hardware/software partitioning with ASIC and system architects while remaining hands-on in critical implementation work.
Set the PHY/link-level modeling and performance-validation approach across subsystems. Establish representative NTN scenarios, performance and power budgets, and acceptance criteria, and resolve architecture tradeoffs using simulation and implementation evidence.
Guide the firmware architecture for real-time processing, memory, data movement, and accelerator control. Co-design low-power operation with ASIC architects, including hardware/software partitioning and power-state coordination; implement or optimize critical functions and resolve performance, power, or integration issues spanning multiple subsystems.
Establish consistent reference-model, fixed-point, and test-vector practices across the modem PHY, enabling ASIC design and verification teams to trace requirements to expected behavior and reproduce discrepancies.
Contribute to SystemC transaction-level modeling (TLM) and high-level synthesis (HLS) development, including synthesizable implementations, with guidance from engineers experienced in these flows.
Lead DSP software and model contributions to pre-silicon verification and first-silicon bring-up across subsystems. Identify integration risks, agree validation priorities with design and verification leads, and drive resolution of issues spanning algorithms, firmware, and hardware.
Lead cross-team technical decisions and architecture reviews, mentor engineers across seniority levels, and guide implementation sequencing and dependency resolution through prototype, tapeout, and silicon validation.

What you bring to this role:

Demonstrated depth in communication DSP and modem architecture, with a record of resolving difficult performance and implementation tradeoffs across interacting PHY subsystems.
Ability to implement and debug numerical algorithms in C/C++, and to use Python or MATLAB for simulation, analysis, and test automation.
Deep practical knowledge of 5G NR PHY implementation and relevant 3GPP specifications, with the ability to assess NTN requirements and translate them into coherent architecture, interfaces, and validation criteria.
Demonstrated experience converting floating-point algorithms to fixed-point implementations, selecting numerical precision, and validating performance against a reference model.
Demonstrated ability to architect and deliver embedded modem software across programmable processors and hardware accelerators, supported by hands-on implementation, optimization, and integration work. Experience guiding low-power ASIC/firmware co-design, allocating power budgets, and evaluating architecture tradeoffs against power estimates and hardware measurements.
Ability to build reproducible tests, use version control, document technical assumptions and results, and explain discrepancies during code and design reviews.
Evidence of technical leadership across multiple PHY subsystems, including hardware/software architecture decisions and delivery through pre-silicon validation and silicon bring-up; ability to resolve cross-team technical disagreements using clear analysis and test evidence.
Typical background: BS with 10+ years, MS with 7+ years, or PhD with 5+ years of relevant experience in DSP, wireless communications, or embedded modem development, with a degree in Electrical Engineering, Computer Engineering, or a related field; equivalent demonstrated expertise is also welcome. These are guidelines, not mandatory minimums. Relevant doctoral research may count toward experience; demonstrated implementation, delivery, and technical leadership capability remains essential.

Bonus points for the following:

Experience establishing SystemC TLM or synthesizable HLS flows across teams, including model fidelity, hardware/software partitioning, implementation tradeoffs, and correlation with RTL or silicon results.
Experience leading 5G NR NTN modem development or resolving satellite-specific acquisition, synchronization, Doppler, and timing challenges through simulation and hardware validation.
Experience taking modem functions through pre-silicon verification and silicon bring-up, including correlation of simulation results with hardware measurements.
Experience with 5G NR MAC, PHY/MAC interfaces, scheduling interactions, or HARQ procedures.
Experience implementing and optimizing algorithms on vector DSPs, including SIMD intrinsics, vectorization, and efficient memory access.
Experience validating ASIC power-management features through firmware, including clock or power gating, retention, and sleep/wake transitions under real-time constraints.

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.