Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SoC Architecture team is involved in  SoC‑level designs for emerging memory/storage solutions and validates each design’s feasibility with hands‑on RTL implementation. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

SoC Architect team proposes multiple SoC level architecture candidates for emerging memory/storage solution and demonstrate that the proposed architecture is viable through hands-on RTL implementation

Job ID: 42976

Location: Daily onsite presence at our Folsom office in alignment with our Flexible Work policy

• Define SoC architecture and microarchitecture for advanced memory subsystem solutions
• Own RTL design and implementation of complex digital logic using SystemVerilog/Verilog
• Derive SoC integration including memory subsystems, high-speed interfaces, clocking, reset, power, and configuration infrastructure.
• Collaborate with architecture, firmware, and verification teams to deliver high-quality SoC designs.
• Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues.
• Support pre-silicon validation and post-silicon bring-up through root-cause analysis and debugging
• Optimize system performance, power, area, and timing through architectural tradeoff analysis.
• Contribute to design documentation, block specifications, and design reviews.

What You Bring

• BS (MS or Ph.D preferred) in Computer/Electrical Engineering or Computer Science with 15+ years of SoC architecture and RTL development experience preferred.
• Deep understanding of modern DRAM technologies, including architecture, timing, memory protocols, training, and controller/PHY interactions.
• Experience designing complex SoCs with memory subsystems and high-speed interfaces.
• Solid understanding of performance, latency, bandwidth, power, area, and timing optimization.
• Experience supporting design verification, debugging simulation/emulation issues, and collaborating with verification teams.
• Experience of FPGA prototyping and silicon bring-up is a plus.
• Strong technical leadership, communication, and problem-solving skills. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.

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