Principal IC Package Design Engineer

Principal IC Package Design Engineer

Summary:

We are seeking a visionary and deeply technical Principal IC Package Design Engineer to lead the architecture, design, and execution of advanced packaging solutions for our next-generation Ethernet switches and PHYs. You will be responsible for the entire package lifecycle—from early-stage feasibility and architectural definition to detailed layout, signal/power integrity (SI/PI) co-design, thermal management, and mass production release.

This role requires a blend of deep technical expertise in advanced packaging technologies (e.g., Flip-Chip BGA, high-density substrates) and the leadership capability to collaborate across Silicon Design, Systems/PCB, Reliability, and external OSAT vendors.

Key Responsibilities

• Package Architecture & Feasibility: Lead the definition of package concepts, substrate stack-ups, bump/ball maps, and pinouts to optimize for system cost, electrical performance, and thermal constraints.
• Detailed Package Design: Execute complex, high-speed, multi-layer package layouts (FCBGA, FCCSP, SiP) utilizing industry-standard EDA tools.
• SI/PI & Thermal Co-Design: Partner closely with Signal/Power Integrity and Thermal engineers to ensure package designs meet stringent targets for high-speed SerDes (56G/112G+), power delivery networks (PDN), and thermal dissipation.
• Substrate Design Integration: Define design rules and manage substrate layout, routing optimization, and manufacturing constraints (DFM/DFA).
• OSAT & Vendor Management: Drive technical engagements with leading substrate suppliers and OSATs. Evaluate vendor capabilities, negotiate design rules, and resolve manufacturing/assembly issues during NPI (New Product Introduction) and production ramp.
• Cross-Functional Collaboration: Act as the bridge between Silicon IC Design and System/PCB teams to ensure seamless chip-package-board co-design and optimization.
• Technology Roadmap: Stay at the forefront of semiconductor packaging trends (e.g., advanced organic substrates, glass substrates, co-packaged optics) to influence Ethernovia’s long-term hardware roadmap.

Qualifications & Skills

Required Experience:

• Education: B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
• 10+ years of direct experience in IC package design and architecture, ideally within high-speed networking, automotive electronics, or high-performance computing (HPC).

Technical Expertise:

• Advanced Packaging: Proven track record of delivering high-volume, complex Flip-Chip BGA (FCBGA), System-in-Package (SiP), and multi-chip module (MCM) designs.
• EDA Tools: Expert proficiency in package design suites such as Cadence Allegro Package Designer (APD), SiP Layout, or Synopsys 3DIC Compiler.
• Signal & Power Integrity Foundations: Strong understanding of electromagnetic theory, transmission lines, crosstalk, and PDN concepts. Familiarity with extraction tools (Ansys HFSS/Q3D, Cadence Clarity) is highly desirable.
• Manufacturing Knowledge: Deep understanding of substrate fabrication processes, assembly line limits, and automotive-grade reliability standards (e.g., AEC-Q100 guidelines).

Leadership & Soft Skills:

• Strong problem-solving abilities with a data-driven approach to architectural trade-offs (e.g., performance vs. cost vs. yield).
• Excellent communication skills, with the ability to articulate complex packaging constraints to cross-functional executives and external partners.

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $265,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

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