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San Jose, California, United States
Onsite
About the Role
Altera is seeking a Principal High-Speed Interface / Silicon Design Engineer to lead the architecture, design, integration, and verification of advanced high-speed interface IP for next-generation FPGA devices. In this role, you will serve as a senior technical authority for high-speed digital interfaces and silicon design, working across architecture, RTL design, verification, PHY/PCS integration, and system-level implementation.
The ideal candidate brings deep expertise in PCI Express and other high-speed serial interfaces, with hands-on experience developing complex RTL and silicon IP from architecture through implementation and validation. Experience with PCIe, PHY/PCS, MIPI/MPHY, HDMI, USB/DisplayPort, high-speed equalization, and PAM4 technologies is highly valued.
This role will partner closely with architecture, analog/PHY, verification, FPGA, software, and system teams to deliver robust, high-performance interface solutions for Altera's next-generation FPGA platforms.
Responsibilities
Lead the architecture and RTL design of complex high-speed interface IP and subsystems, with a primary focus on PCIe and related high-speed serial technologies.
Provide technical leadership for all current and future-generation high-speed interface architectures, including emerging high-bandwidth serial technologies
Define and develop PCIe MAC, PCS, link, and subsystem functionality, including high-speed interface protocols, link initialization, equalization, lane management, and related control logic.
Drive end-to-end technical ownership of high-speed interface designs from architecture and microarchitecture through RTL implementation, verification, synthesis, timing analysis, and silicon validation.
Develop and integrate high-speed digital interfaces with PHY and analog IP, collaborating closely with PHY designers on interface requirements, calibration, equalization, and system-level performance.
Lead design activities involving high-speed equalization and signal-processing techniques, including Tx FFE, Rx FFE, CDR, DFE, LMS, and related equalization methodologies.
Analyze and resolve complex design issues involving CDC, lint, synthesis, STA, formal verification, RTL quality, and subsystem integration.
Collaborate with verification teams to define verification strategies and drive functional, formal, simulation, FPGA, testchip, and silicon validation activities.
Serve as a technical interface between digital design, PHY/analog, verification, architecture, software, and product engineering teams.
Mentor senior and junior engineers and provide technical direction on architecture, RTL design methodology, design reviews, and problem resolution.
Lead technical design reviews and influence architecture and implementation decisions across multiple engineering teams.
Drive continuous improvements in high-speed interface design methodologies, verification strategies, and IP reuse.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $303,250 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
12+ years of experience in ASIC, SoC, FPGA, silicon, or digital IC design.
8+ years of experience designing and developing high-speed interface IP or digital subsystems, including hands-on RTL development using Verilog and/or SystemVerilog.
5+ years of experience with PCI Express, PCIe PHY/PCS, MAC, Link, or related high-speed serial interface technologies.
3+ years of experience architecting or leading complex silicon IP or subsystem designs through multiple stages of the development lifecycle.
3+ years of experience working with high-speed interface technologies such as MIPI/MPHY, HDMI, USB, DisplayPort, or comparable serial interfaces.
3+ years of experience with digital implementation and signoff methodologies, including lint, CDC, synthesis, static timing analysis, and/or equivalence checking.
Experience with high-speed equalization or signal-processing techniques, including technologies such as PAM4, FFE, DFE, CDR, LMS, or related methodologies.
Experience providing technical leadership, architecture ownership, design reviews, and mentorship for complex engineering projects.
Preferred Qualifications
Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Experience with PCIe Gen5/Gen6 or higher-speed PCIe architectures.
Experience with PAM4-based high-speed interfaces and digital signal-processing implementations.
Experience integrating digital logic with analog PHY IP, including PLL, CDR, DFE, equalization, and related circuitry.
Experience with MATLAB/Simulink or equivalent modeling environments for high-speed interface analysis and verification.
Experience with formal verification and SVA, including tools such as JasperGold.
Experience with FPGA-based prototyping, testchip development, post-silicon validation, or ATE.
Strong understanding of high-speed interface protocols, link training, lane management, equalization, and PHY/PCS architectures.
Demonstrated ability to lead highly complex technical programs involving multiple engineering disciplines.