Principal ASIC/SoC Validation Lead - Photonic Fabric

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Principal Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role combines hands-on silicon bring-up and debug with technical leadership of validation activities, including test planning, methodology, and coordination across design, DFT, firmware, and product/test engineering.

What You Can Expect

• Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces, covering functionality, performance, power, margining, and interoperability.  
• Lead silicon bring-up and lab validation, including platform bring-up (boards, power, clocks, resets) and interface‑level validation for CXL/PCIe/DDR/HBM/SerDes.  
• Provide technical direction to other validation engineers, including test plan reviews, debug guidance, and prioritization of tasks and issues.  
• Configure and operate advanced lab equipment: high‑bandwidth oscilloscopes and probes, logic analyzers, PCIe/CXL protocol analyzers, BERTs, pattern generators, power supplies, electronic loads, and environmental chambers.  
• Drive development of lab automation and data analysis infrastructure (Python, TCL, shell, MATLAB or similar) to improve coverage, throughput, and reproducibility.  
• Analyze large data sets to characterize high-speed links and memory interfaces (BER, eye diagrams, jitter, margins, throughput, latency, power) and translate findings into design and validation recommendations.  
• Lead root-cause investigations across silicon, firmware, board design, and test setup; coordinate cross-functional issue closure with design, DFT, firmware, and product/test engineering.  
• Own documentation of validation methodologies, lab setups, and results; communicate status, risks, and mitigation plans to project leadership.  
• Mentor and coach junior validation engineers, helping build a strong, scalable lab validation team and best practices.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR  Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
• Typically 5+ years of industry experience in silicon or system validation, including hands-on lab work.  
• Strong expertise in at least two of the following: CXL (2.0/3.x), PCIe (Gen4/Gen5/Gen6), DDR (DDR4/DDR5), HBM (HBM2/2E/3), high-speed SerDes.  
• Proven experience leading bring-up and validation of complex ASIC/SoC products from first silicon through production.  
• Deep hands-on experience with lab equipment (oscilloscopes, protocol analyzers, logic analyzers, BERTs, power supplies, etc.) and high-speed measurement techniques.  
• Strong scripting and lab automation skills (e.g., Python, TCL, shell, MATLAB) for test control and data analysis.  
• Demonstrated ability to drive cross-functional debug and closure, with clear communication of complex technical issues.  

Preferred Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.  
• Experience leading small validation teams or acting as technical lead on multi‑site projects.  
• Familiarity with DFT features (scan, BIST, JTAG) and their use in bring-up and debug.  
• Experience with signal integrity/power integrity concepts and working with SI/PI or board design teams.  

Expected Base Pay Range (USD)

150,680 - 225,700, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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