As a RTL Design Hardware Engineer within the Software Performance and Integration group, you are expected to work on the RTL underpinning Altera's System-on-Chip integration tool, Platform Designer, FPGA Debug Environment Tools such as SignalTap and System Console. The goal of this team is to implement powerful embedded hardware systems using a straightforward flow from design creation through debugging and performance optimization. The team is responsible for development of RTL for various soft IPs, including an on-chip Memory Mapped Interconnect ( AXI/APB/AHB/Avalon) , streaming protocols IPs ( AXI / Avalon ), debug IP such as signaltap, ISSP, ISMCE, bridge and adapter IPs and supporting a full stack of tools which assemble these IPs in interesting and dynamic ways.
As a Hardware Engineer in this position, you will need to be excellent at digital design with expertise in VHDL/Verilog/System Verilog with responsibilities as listed (but not limited to) below:
Lead a team of dedicated RTL design Engineers to build soft IPs for Altera FPGAs
Coming up with newer versions of on-chip transfer protocols aimed for high speed for our latest FPGA’s using hyperflex architectures
Developing new Interconnect topologies to maximize data transfer throughput over long distances
Extending support for industry standard Memory Mapped and Streaming protocols
Developing robust IP and networks which customers use in mission critical debug environments
Work with RTL Design Verification team to review and supervise the verification of the IPs developed
The RTL design engineer will have a direct influence on our customers and the adoption of our products, with tasks including the following:
Work closely with developers across software, IP and embedded engineering to ensure we develop design flows that meet our customers' needs
Guide IP release content, and serve as a liaison with the support, field, marketing, and product planning organizations
Research, define, and validate key customer use cases
Create reference RTL designs and regressions tests
Use Altera FPGA design tools like our customers to identify usability and productivity problems or missing features
Qualifications:
BS/MS/PhD degree in Electrical/Computer/Software Engineering or equivalent and 10+ years of relevant industry experience
Strong understanding and knowledge of digital design/Timing Closure concepts/Fundamentals of Verification/Hardware Debug
Strong experience in Verilog and System Verilog
Understanding of Computer Architecture/ARM Based Bus Protocols
Understanding of other communication protocols will be plus
Knowledge of Quartus or Vivado tool flow is a plus
Tcl, Perl, and/or Python scripting skills
Dedication to customer experience and usability
Strong written and oral communication skills
Ability to influence across organization boundaries