Oregon Hillsboro, United States of America
Onsite
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
Altera is seeking a highly motivated Senior Design Verification Engineer to join our FPGA Silicon Engineering team. In this role, you will be responsible for planning, developing, and executing comprehensive verification strategies for complex FPGA intellectual property (IP), subsystems, and SoC-level designs. You will collaborate closely with architecture, design, firmware, emulation, and validation teams to ensure first-pass silicon success and deliver high-quality products to our customers.
The ideal candidate possesses deep expertise in modern verification methodologies, strong debugging skills, and a passion for solving complex technical challenges. This position offers the opportunity to work on cutting-edge FPGA architectures and influence verification excellence across multiple product generations.
Responsibilities:
Define and execute verification plans for complex FPGA IPs, subsystems, and SoC components.
Develop scalable SystemVerilog/UVM-based verification environments and reusable verification infrastructure.
Create constrained-random, directed, and coverage-driven test strategies to validate design functionality.
Develop assertions, checkers, scoreboards, and protocol monitors to improve verification quality and efficiency.
Drive verification closure through functional, code, assertion, and toggle coverage analysis.
Perform RTL debugging and root-cause analysis of functional failures.
Collaborate closely with design, architecture, firmware, and validation teams to resolve issues throughout the development lifecycle.
Support emulation, FPGA prototyping, and post-silicon debugging activities when required.
Participate in design reviews and contribute to verification methodology improvements and best practices.
Mentor junior engineers and provide technical leadership within the verification team.
What We Offer
Opportunity to work on industry-leading FPGA technologies.
Collaborative environment with highly talented engineering teams.
Competitive compensation, bonus, and benefits packages.
Professional development and career growth opportunities.
The ability to influence next-generation programmable technology products used by customers worldwide.
Salary Range
The pay range below is for the United States market only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$169,000 - $240,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 10+ years of experience in Design Verification, ASIC, FPGA, or SoC development; OR Master's degree and 8+ years of experience; OR PhD and **6+ years of experience.
10+ years of hands-on experience developing and executing verification plans for complex digital designs, IPs, subsystems, or SoCs.
10+ years of experience using SystemVerilog for verification and testbench development.
8+ years of experience developing and maintaining UVM-based verification environments for block-level and/or system-level verification.
10+ years of experience applying constrained-random, assertion-based, and coverage-driven verification methodologies.
10+ years of experience debugging RTL and verification environment issues using industry-standard simulation and waveform debug tools.
5+ years of experience developing verification automation, infrastructure, or productivity tools using Python, Perl, Tcl, Shell, or similar scripting languages.
Demonstrated experience delivering verification closure on at least two full ASIC, FPGA, or SoC product development cycles from architecture through tapeout.
Experience analyzing and driving closure of functional and code coverage metrics across complex verification environments.
Proven ability to work effectively in cross-functional teams consisting of design, architecture, firmware, emulation, and validation engineers.
Preferred Qualifications
Experience verifying FPGA architecture components, programmable fabric, interconnects, memory subsystems, or high-speed interfaces.
Knowledge of industry-standard protocols such as PCIe, Ethernet, CXL, DDR, LPDDR, HBM, AXI, or AMBA.
Experience with formal verification tools and methodologies.
Experience with emulation platforms, FPGA prototyping, or hardware-assisted verification.
Familiarity with low-power verification methodologies.
Prior experience leading verification efforts for complex IPs or SoCs.
Experience working in a silicon product development environment from architecture through production.