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Mountain View, California, United States
Onsite
At Rhoda AI, we’re building the next generation of generalist intelligent robots. We own the full robotics stack from high-performance hardware and robot systems to the infrastructure and state-of-the-art foundation world models that control our robots. Our robots are designed to be generalists capable of operating in complex, real-world environments and handling long-tail edge cases, made possible by our cutting edge research and end-to-end system design. We've raised over $450M and are investing aggressively in model research, infrastructure, hardware development, and manufacturing scale-up to make generalist robotics a reality.
Running large multimodal foundation models for a growing fleet of robots is expensive. We can't rely on one hardware vendor or the most expensive accelerators. We're looking for an Inference Optimization engineer to make Rhoda's models run fast, correctly, and cheaply on a wide range of hardware: AMD Instinct GPUs, Google TPUs, wafer-scale and dataflow accelerators, consumer GPUs like the RTX 5090, and the Jetson/Thor-class compute on our robots. You'll decide which chip runs which workload, and then make sure it runs well there. You'll work closely with the research, robotics, and infrastructure teams.
Own cost-efficient inference end-to-end. Make Rhoda's foundation models (vision, video, language, proprioception, action) faster and cheaper to run, measured in latency, throughput, and cost per inference.
Port and optimize models for non-NVIDIA and lower-cost hardware. This includes AMD (ROCm, HIP, MIOpen/hipBLASLt, Composable Kernel), TPU (XLA, JAX, Pallas, PyTorch/XLA), wafer-scale and dataflow accelerators (their SDKs and compilers), and consumer Blackwell GPUs such as the RTX 5090 (FP8/FP4, small memory, multi-GPU setups over PCIe).
Own on-robot inference. Deploy and optimize models on Jetson/Thor-class embedded compute under tight latency, power, thermal, and memory limits, and decide how work is split between the robot and the cloud to meet real-time control requirements.
Evaluate hardware rigorously. Build cost/performance models (perf/$, perf/W, memory capacity and bandwidth, interconnect) for each chip and model family. Write clear recommendations on which hardware to buy or rent for serving, offline evaluation, and on-robot use.
Build hardware-portable optimizations. Write and tune kernels that work across vendors where possible (Triton, Pallas, MLIR-based compilers) and vendor-specific ones where the speedup justifies it. Handle attention, KV cache, memory layout, and fused operators on every backend.
Apply model compression for constrained hardware. Use quantization (INT8, FP8, FP4/MX formats, AWQ/GPTQ), pruning, distillation, and model or tensor parallelism so models fit and perform well on chips with less memory or limited data-type support.
Keep results correct and consistent across backends. Build tests that check numerical parity, policy quality, and robot-relevant behaviour, so a model gives the same results whichever chip it runs on.
Build benchmarking and regression infrastructure across hardware. Track latency baselines, throughput curves, and cost per inference for every model version on every target, with automated detection of regressions.
Work with research engineers to design models that stay efficient and portable from the start, for example by avoiding operators that only exist on one vendor's hardware.
2+ years of experience in inference optimization, ML systems, ML compilers, or a closely related field.
Deep hands-on experience with PyTorch.
Strong understanding of compute, memory bandwidth, memory capacity, and interconnect bottlenecks, and how they change from one hardware architecture to another.
Experience with model optimization techniques: quantization (INT8/FP8/FP4, AWQ), distillation, pruning, and compilation (torch.compile, XLA, TensorRT, IREE/MLIR, TVM, or vendor compilers).
Familiarity with inference serving frameworks and their support for different hardware (e.g. vLLM on ROCm/TPU, SGLang, JetStream, Triton Inference Server).
Excellent debugging and measurement skills. You can take "this is slow on chip X" or "this costs too much" and turn it into clear bottlenecks, experiments, and validated improvements.
A high-ownership, pragmatic mindset. You care about the total cost of a solution, not just peak benchmark numbers.
Experience optimizing inference for diffusion models.
Production or deep project experience with at least one accelerator stack other than NVIDIA datacenter GPUs: AMD ROCm, Google TPU, wafer-scale and dataflow accelerators, Groq, Tenstorrent, AWS Trainium/Inferentia, Intel Gaudi, or similar, or serious work deploying on consumer GPUs.
Kernel authoring on more than one backend: HIP or Composable Kernel on AMD, Pallas on TPU, Triton on both NVIDIA and AMD, CUTLASS/CuTe.
Contributions to open-source ML compilers or hardware backends (PyTorch, OpenXLA, Triton, vLLM, IREE, TVM).
Experience running inference on wafer-scale systems, TPU pods, or fleets of consumer GPUs.
Hands-on experience with Jetson/Thor-class platforms (TensorRT on Jetson, JetPack, DLA, power and thermal profiling).
Experience with multimodal or video model inference (variable-length sequences, packing/bucketing).
Speculative decoding, continuous batching, disaggregated prefill/decode, or other LLM serving optimizations.
Experience with streaming or low-latency systems for real-time robot control.
Experience working with hardware vendors on driver or compiler bugs and early-access silicon.
Direct impact on cost and scale. Every gain in perf/$ you deliver lowers the cost of serving models and evaluating new ones, and of putting capable models on many more robots.
Strategic influence over hardware. Your benchmarks and recommendations will directly shape which accelerators Rhoda buys and builds on, in the cloud and on the robot.
High ownership on a small, elite team. You'll own the optimization layer that decides how fast and how cheaply our foundation models run in the real world, on every target we use.