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Bengaluru, Karnataka, India
Onsite
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JD for Senior Design Engineer
1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.
4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
6) Logic simulations and detailed timing analysis of key paths in high speed memory design.
7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.
Skill Sets/Prerequisites
1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
2) Experience in Designing and driving one or many Memory Compilers Specifications to final release
3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
7) Experience in Skill/Perl/Python Scripting is a strong plus
8) Experience in Understanding the layout design issues in sub nanometer regime is a must.
9. Expertise in Understanding Memory DFT is a Plus.
10. Masters Degree with 4+ Years or Bachelors Degree with 5+ years
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