Senior Photonics Design Automation Engineer

We are hiring a Photonics PDK Design Automation Engineer to join our team. In this role, you will develop our internal Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between photonics device design and system-level verification. You will develop robust flow ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, EDA tools, applying software engineering rigor to the challenges of photonic hardware design.

Responsibilities

• Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models.
• Develop and maintain custom photonic Layout vs Schematic (LVS) decks across multiple foundry technologies
• Design and test device and parameter extraction for innovative photonic devices
• Troubleshoot and resolve LVS mismatches in complex analog and photonic circuits
• Actively collaborate with design, layout, modeling, and infrastructure engineers to deliver high impact tape-outs
• Automated Verification: Implement regression testing and Continuous Integration (CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic.
• Contribute to other PDK, DRC, and automation projects as needed

Qualifications

• Masters or PhD in Electrical Engineering, Computer Engineering, Photonics, or related field.
• Prior experience in performing physical layout using foundry-provided process design kits (PDKs), adhering to specific design rules and constraints.
• Experience with photonics layout
• Python based layout experience. Comfortable with object-oriented programming and scientific libraries (NumPy, SciPy).
• Experience writing software and scripts in languages such as Python, SVRF, Tcl, Bash, and SKILL
• In-depth knowledge of integrated photonic devices, analog devices, and parasitics
• In-depth knowledge of foundry process (SOI, etching, implants, metal stacks)
• Proficiency with Linux environments, advanced version control (Git), and software engineering best practices
• Demonstrated strong problem solving skills for problems without obvious solutions

Preferred Qualifications

• 1+ years experience in LVS deck development for Siemens Calibre, Cadence Pegasus, and/or Synopsys IC Validator, experience troubleshooting and resolving LVS mismatches in complex circuit designs 
• Proficiency with python-based layout tools such as gdstk, GDSFactory, and KLayout
• Experience with Git setup, version control, unit testing (pytest), and CI/CD workflows.
• Experience with DRC deck and rule development
• Experience working on large-scale designs using industry standard environments such as Cadence Virtuoso
• Excellent communication skills, with a demonstrated ability to collaborate effectively with multidisciplinary teams
• Strong project execution skills, with the ability to handle multiple priorities and meet project milestones