Senior/ Staff Formal Verification Engineer

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

• Own and develop formal verification environments from scratch through to sign-off
• Apply formal verification methodologies and strategies to prove the correctness of intricate designs
• Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
• Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
• Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
• Architect and develop generic, common formal functions and properties to be reused across multiple projects

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related technical field
• 4+ years of hands-on experience in Formal Verification within semiconductor companies
• Deep expertise in formal verification methodologies, tools, and flows
• Strong understanding of RTL design and verification principles
• Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
• Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving

Preferred Qualifications

• Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle
• Experience with SystemVerilog UVM-based design verification
• Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)
• Background in high-speed serial interface verification