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San Jose, California, United States
Onsite
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
You will be working in Design Automation group for the technical owner of Static Timing Analysis flows and timing modeling methodology across Altera's ASIC, Custom and Semi-Custom IP designs — and the leader of the small team that delivers it.
Real architectural latitude. We are in the middle of a genuine modernization: standing up next-generation characterization flows, and onboarding timing sign-off into a new unified flow environment. There is meaningful greenfield work here, not just incremental maintenance.
Breadth you rarely get in one seat. Block-level, full-chip, transistor-level and FPGA timing collateral all live in this domain. Few timing DA roles anywhere span SPICE-level circuit simulation and cell characterization at one end through customer-facing FPGA timing deliverable flows at the other.
A seat at both tables. You will represent the timing DA domain with design team leads, physical design, technology enablement and QRE partners in cross-functional methodology forums and working groups, and you will drive our engagements with the major EDA vendors — evaluating capabilities, escalating what blocks us, and shaping roadmaps. Being the bridge between what our designers need and what the tools can actually do is the heart of this role. It reports directly to the DA engineering director for the domain, so your technical judgment carries without layers of translation.
Real production flows, real users. This is a hands-on CAD role: you will develop and release production-grade flows, regressions and automation, then support the design teams running them — triaging tickets, debugging timing issues alongside designers on live tape-outs, and delivering the training and documentation that make the methodology stick. The best ideas in this domain come from sitting with the people closing timing under schedule pressure.
Colleagues whose expertise reaches well beyond STA. You will work alongside a small group of deep specialists whose domains span circuit simulation and optimization, custom cell characterization and Liberty model generation, FPGA timing model generation, and timing derate and reliability methodology. Being the technical lead here means influencing the whole chain from transistor-level simulation through characterization to the timing models our design teams and our FPGA software toolchain ship — not just the analysis step in the middle. If you have ever wanted your timing decisions to reach all the way back into how the models are built, this is that seat.
Room to grow your own technical range. You will set technical direction and mentor engineers on timing methodology, and you should expect to learn as much from the characterization and circuit-simulation depth around you as you bring to it. You will also have a genuine voice in how we invest in the timing domain going forward.
AI where it actually pays off. We are actively applying AI and ML inside our design automation flows — runtime and resource prediction, corner reduction, knowledge capture from debug. If you want to bring those techniques into timing, characterization or model generation, you will find an organization already leaning in.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$187,000 - $270,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
10+ years of professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field, with significant hands-on experience developing and deploying production design automation or timing flows.
10+ years of experience working with Static Timing Analysis (STA) and timing sign-off methodology, including timing constraints, multi-corner multi-mode (MCMM) analysis, crosstalk, on-chip variation (OCV), timing derates, and advanced process-node timing challenges.
10+ years of experience with industry-standard timing analysis, cell characterization, and/or SPICE circuit simulation tools, with the technical depth to evaluate tool capabilities and make methodology decisions.
10+ years of experience developing automation and software for engineering workflows, including strong proficiency with Python, Tcl, shell scripting, or similar languages, along with a solid understanding of algorithms, data structures, and production-quality software development practices.
Demonstrated experience owning and releasing production-grade DA/CAD flows, including flow architecture, regression infrastructure, automation, validation, deployment, maintenance, and user support.
Demonstrated technical leadership in a design automation or timing domain, including setting methodology direction, driving complex technical decisions, establishing best practices, and mentoring engineers without requiring formal management authority.
Proven experience partnering directly with ASIC, custom IC, physical design, circuit design, or other semiconductor design teams to define methodology requirements, deploy production flows, resolve technical issues, and support designs through tape-out or sign-off.
Demonstrated ability to lead cross-functional technical initiatives and influence engineering decisions across geographically distributed teams, including collaboration with design, physical design, technology/process, reliability, and EDA vendor organizations.
Experience owning block-level and/or full-chip STA methodology and timing closure flows through multiple production tape-outs.
Advanced experience with cell characterization and Liberty model generation, including LVF, POCV, statistical timing, or related variation-aware modeling methodologies.
Experience with transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flows.
Experience developing or supporting FPGA timing models, timing collateral, or customer-facing timing deliverables.
Experience with timing reliability, aging, derating, electromigration, or other reliability-aware timing methodologies.
Experience with advanced-node timing challenges involving variation, signal integrity, crosstalk, multi-voltage designs, low-power methodologies, or complex MCMM sign-off requirements.
Experience evaluating, deploying, and influencing roadmaps for major commercial EDA tools and vendors, including the ability to identify tool gaps and drive technical escalations.
Experience applying AI/ML techniques to design automation, including runtime/resource prediction, timing optimization, corner reduction, knowledge capture, or automated debug.
Experience leading technical roadmaps, methodology modernization, or greenfield CAD/EDA infrastructure initiatives across multiple engineering organizations.
Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.