We are seeking highly skilled and motivated System-on-Chip & FPGA Performance Modeling architects. Focus will be on developing and simulating models of performance critical hardware components, their interplay and the overall architectures of our next generation FPGAs. Role is within Architecture team and involves close collaboration with fellow architects and designers. Role requires early design space exploration across potential architectures at FPGA level, interconnect level, and within subsystems, in order to converge on best-in-class Power, Performance and Cost as a function of features. The individual will own performance through the development lifecycle from concept through design, all the way to silicon validation. This involves cross-team and functional collaboration covering architecture exploration, TLM model development, workload analysis, performance evaluation, correlation to cycle-accurate RTL and Silicon, and empowerment of customers' to evaluate performance of their FPGA systems.
Requires strong C++ and SystemC coding skills for developing TLM2.0 performance models, testbenches and workloads.
Knowledge of data movement within modern SoC architectures including interconnect, DDR, PCIe, Ethernet and embedded processors.
Knowledge of state-of-the-art Performance modeling methods with tight coupling to realizable performance in final product.
FPGA knowledge is a plus but not essential.
Bachelors, Masters, or PhD degree in Electrical Engineer, Computer Engineering, Computer Science or a closely related field.