At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Duties:
- Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
- Lead and drive customer engagement to solve verification challenges with leading edge technologies and methodologies such as vManager.
- Cooperate with key customers to deploy advanced verification and debug solutions and follow up with the development groups.
- Discuss priorities and review functional specification for the customer requirements.
- Educate the field on new solution and methodologies in cooperation with the Business Unit.
- Understand customer challenges and drive requirements to the development teams.
- Understand priority, value, and timeliness of the ultimate solution.
- Support the development of key verification flows and methodologies to improve the Smart Verification Solutions at Cadence, focusing on the unique requirements of the design and verification community.
- Help develop strategy and technology roadmaps for product engineering Smart Verification flows and related applications that drive the value of the full Cadence verification suite.
- Write requirement specifications and review functional specifications to ensure relevant solutions are provided to customers.
- Some telecommuting permitted.
- Must be available to work on projects at various, unanticipated sites throughout the United States and internationally.
Qualifications:
- Master’s degree in Electronic Engineering, Electrical Engineering, or related field.
- Minimum eight (8) years of experience in the job offered or in a related engineering occupation.
- EDA tools and verification solutions including deploying advanced verification and debugging solutions using Universal Verification Methodology (UVM)
- Functional verification flows including coverage driven verification and constrained random testing
- Design and verification languages and methodologies including SystemVerilog, Very High-Speed Integrated Circuit Hardware Description Language (VHDL), C/C++, Universal Verification Methodology (UVM)
- Worked on verification Methodologies using vManager and UNR (Coverage unreachability)
- Client and server technologies, database architectures, big data and machine learning
- Building unique examples which replicate the customer scenarios, worked on the new technologies and methodologies using Powerpoint, Register-Transfer Level (RTL) design, and test bench (TB)
- Must be available to work on projects at various, unanticipated sites throughout the United States and internationally.
The annual salary range for California is $216,091 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the base salary range is a guideline, and individual total compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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