Sr Staff CPU Design Engineer

At MIPS, a GlobalFoundries company, we’re shaping the future of compute architecture with advanced IP that powers a wide range of applications. We take a disciplined, methodical approach to designing scalable, energy-efficient solutions that meet demanding power, performance, and area goals.

Our team spans from architecture, performance modeling, design, verification, implementation to software and software optimization for our customers. The team thrives on collaboration, technical depth, and a culture of mutual respect. We value diverse perspectives and practical experience, and we know that excellence is built through thoughtful teamwork and a commitment to the highest engineering standards.

We’re seeking a Senior Staff CPU Design Engineer with prior experience in creating structural RTL for one of the following: CPU, GPU, DSP, Interconnects, memory controllers or compute accelerators.

As part of our team, you’ll have the opportunity to take ownership of CPU functional blocks and implement RTL, and work with verification and physical design engineers to ensure adherence to functional and physical project requirements.

Essential Responsibilities:

As a Sr Staff CPU design engineer you own or participate in the following:

• RTL design of one or many functional blocks based on the microarchitectural specification. Ownership includes the RTL design, implementation and convergence of the block to project requirements (performance, timing, power, area, schedule)
• Support of the verification team for test bench development, test plan development and test content development, including performance verification
• Work with physical design teams, and design for testability teams to implement and converge physical design and testability

• Experience in structural data path and/or control logic design
• Experience with Verilog, System Verilog, or VHDL
• Experience with commercial simulators and debugging tools
• Good verbal and written communication skills to interface with performance modeling, verification and physical design team

Preferred Qualifications

• Experience with timing convergence
• Experience with low power design techniques
• Experience using scripting languages and regular expressions
• Programming experience with assembly, C, or C++

Expected Salary Range

$126,000.00 - $218,000.00

The exact Salary will be determined based on qualifications, experience and location.