This is a hybrid role with four days per week at Cisco’s Yerevan office.
Meet the Team
Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions.
Your Impact
This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco’s Silicon One Engineering team offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization.
Contribute to the development, maintenance, and automation of STA signoff flows for complex SoC designs.
Assist with timing constraint development (SDC) and validation for multi-mode, multi-corner analysis.
Develop and enhance automation scripts and utilities (TCL, Python) to streamline timing flows and improve engineering efficiency.
Work with senior engineers to support timing closure during the design cycle, assisting with debug and issue triage.
Collaborate with RTL, DFT, and physical design teams to align on design intent and STA best practices.
Assist in the evaluation and deployment of new tool features and methodologies from EDA vendors.
Contribute to documentation, training materials, and internal tool support for design teams.
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
4+ years of experience in ASIC or SoC design with a focus on STA, CAD automation, or physical design methodology.
Solid understanding of STA fundamentals: setup/hold, clock skew, OCV, path exceptions, MMMC analysis.
Experience using timing tools such as PrimeTime, Tempus, or similar.
Proficient in scripting languages such as TCL and Python.
Familiarity with physical design flows, synthesis, and timing ECOs is preferred.
Strong analytical and problem-solving skills with attention to detail.
A team player with good communication skills and a collaborative attitude.
Preferred Qualifications
Exposure to large-scale SoC design flows, especially in networking or communications domains.
Experience working in a Unix/Linux-based development environment.
Knowledge of EDA tool environments, job scheduling systems, or version control systems (e.g., Git, Perforce).
Enthusiasm for continuous learning and improving automation and productivity.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.