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Bengaluru, Karnataka, India
Onsite
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
As a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation, timing closure, and structural backbone of our next-generation designs. In this role, your primary focus will be mastering the critical intersection of global signal planning, advanced clocking architectures, and high-performance physical design interconnects. You will be responsible for translating complex RTL into high-performance silicon implementations by analyzing the design from both a physical layout and a circuit-level perspective—ensuring that long-wire signal distribution and clocking networks inherently support robust electrical performance.
We are looking for a "full-stack" physical design engineer who understands that chip performance relies heavily on efficient distribution networks. You should be the type of engineer who enjoys diving into schematics and microarchitecture to understand how clocking choices impact PPA, how global wire parasitics affect latency, and how transistor-level behavior influences chip-level signal and timing integrity.
Advanced Clock Distribution & Circuit Design: Architect and implement high-speed, low-skew clock distribution networks (e.g., mesh, H-tree, hybrid topologies). Apply circuit-level understanding to optimize clock buffers, clock gaters, latches, and multi-source CTS.
Interconnect Physical Design: Manage the physical implementation of global signal planning, including high-speed bus routing, long-wire interconnect span limits, and repeater insertion strategies. Optimize long interconnect paths to mitigate RC delay, wire resistance variations, and routing congestion.
Circuit-Level Timing & Noise Integrity: Leverage a strong fundamental grasp of RC interconnect modeling and transistor-level behavior to resolve deep-submicron physical effects—such as crosstalk delay, Electromigration (EM), and dynamic IR-drop on clock and global signal lines.
Architectural & Circuit Co-Optimization: Partner with RTL and Architecture teams to influence design decisions. Bridge the gap between logic design and circuit reality, identifying bottlenecks early (such as asynchronous clock domain crossings and interconnect span limits) and suggesting structural or microarchitectural optimizations.
Technical Leadership & Signoff: Act as the subject matter expert for interconnect structures, clock planning, and circuit techniques during implementation. Mentor junior engineers and contribute to the evolution of advanced design methodologies and flows.
Experience: 8+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced process nodes (7nm and below preferred).
Clocking & Interconnect Expertise: Deep familiarity with the physical implementation of advanced clocking structures, global interconnect routing, multi-corner multi-mode (MCMM) timing closure, and jitter analysis.
Circuit-Level Understanding: Strong fundamentals in VLSI design, including CMOS circuit behavior, RC delay networks and transistor-level timing/noise concepts.
Tool Mastery: Expert-level proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off tools, with heavy emphasis on CTS, parasitic extraction (RC), and Static Timing Analysis (STA) engines.
Problem Solving: Ability to debug complex timing violations, cross-talk delay, global interconnect routing congestion, and transient IR drop issues with minimal supervision.
Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
In this role, you will be pivotal in driving Power, Performance, and Area (PPA) optimizations across significant design sections, operating at the critical intersection of clock architecture, global interconnect optimization, and circuit integrity. You will have the autonomy to shape the foundational distribution networks in all our designs, working on diverse product lines from extremely efficient edge devices to demanding high-performance platforms. We offer the opportunity to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.