As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
The Role:
Join the SiFive AI/ML Software Team to build the high-performance stack for Next-Gen AI. We are seeking engineers to optimize and deploy LLMs and Generative AI models on RISC-V architectures, spanning from compiler infrastructure to distributed runtime systems.
Responsibilities:
Heterogeneous System Architecture: Design and implement the core compute programming model and device runtime daemon. You will define the orchestration of asynchronous task execution, managed memory hierarchies, and efficient host-device synchronization.
Inference Stack Integration: Lead the deployment of production-grade stacks like vLLM and SGLang on RISC-V. Optimize memory-bound operations, including PagedAttention and sophisticated KV-cache management, within a heterogeneous environment.
Kernel & Compiler Synergy: Enable seamless lowering from Triton/MLIR-based compiler to SiFive hardware-specific extensions. Develop high-performance kernels that push the limits of RISC-V Vector (RVV) and matrix compute units.
Co-design: Collaborate with hardware architects to influence the design of future AI accelerators and micro-architectures.
Requirements
At least 5 years working experiences in the relevant industry and field.
Education: MS/PhD in Computer Science, EE, or a related field.
Programming: Strong proficiency in C++ and Python.
Heterogeneous Computing: Deep understanding of execution models for offloading compute (e.g., familiar with the concepts behind CUDA, ROCm, or OpenCL runtimes).
AI Infrastructure: Practical experience with LLM serving internals (vLLM, SGLang, or TGI). Understanding of how frameworks interact with hardware backends.
Preferred Qualifications
RISC-V Enthusiast: Familiarity with RISC-V Vector (RVV) extensions and the RISC-V software ecosystem.
CUDA Mastery: Deep experience with CUDA C++ and an understanding of the NVIDIA software stack internals.
Open Source Influence: Active contributor to vLLM, SGLang, PyTorch, or the LLVM/MLIR project.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
TaiwanAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.