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Mountain View, California, United States
Onsite
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
In partnership with our engineering leads, you will break down company objectives into actionable milestones across the engineering org. You will own the schedule across the entire silicon development lifecycle. You will surface information in a digestible format so that engineering executives are acutely aware of the current state of the project. You will also help to resolve issues across teams. Your work will ensure we ship on time.
Break down company objectives into actionable milestones across the engineering org.
Own the schedule across the silicon development cycle: architecture, micro-architecture, RTL generation, verification, logic synthesis, design for test, physical design, physical verification, tapeout, packaging, post-silicon testing, bring-up and post-silicon validation.
Coordinate these efforts across our teams in Mountain View, New York, London, Zurich and Copenhagen.
Define metrics, create dashboards and other mechanisms to surface information and track progress.
Identify and mitigate risks to delivery schedules and quality.
Synthesize complex technical status, trade-offs, and risks into clear updates for executive leadership.
10+ years in semiconductor development, including 3+ years as a TPM or program lead on complex ASIC or SoC architectures.
Excellent communication and stakeholder management skills; ability to influence without authority.
Experience in companies with complex software/hardware integration.
Proven track record managing internationally distributed engineering teams.
Proficiency with program management tools such as Jira, Asana or Linear.
Experience with every element of the silicon life-cycle from architecture and RTL generation to verification, tapeout, bring-up and post-silicon validation.
Ability to think out-of-the-box to find solutions.
Ph.D. in an electrical engineering discipline.
Familiarity with chiplets and 3D packaging.
Expert at using Linear for program management tracking.
Familiarity with heterogeneous systems used for AI inference.
Experience working with external silicon foundries, Tier II vendors and OSAT vendors.
Experience working at a silicon startup.
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
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