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Jaroměř, Česko
Remote only
This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior ASIC & FPGA Design Engineer based in the United States.
Join a technically advanced engineering environment where you will design and develop high-performance digital and mixed-signal integrated circuits and FPGA solutions.
As a Senior ASIC & FPGA Design Engineer, you will contribute to the full hardware development lifecycle, from architecture and RTL design to verification, implementation, and system integration.
You will leverage your expertise in VHDL, Verilog, and SystemVerilog to build reliable, efficient designs that meet demanding performance and timing requirements.
Working closely with architecture, systems, firmware, and product engineering teams, you will help solve complex implementation challenges and deliver robust hardware solutions.
Your responsibilities will include verification strategy, timing analysis, design optimization, and support for laboratory integration and troubleshooting.
This fully remote contract opportunity offers the chance to apply advanced digital design expertise to technically challenging projects alongside multidisciplinary engineering teams.
The initial contract runs from October 12, 2026, through June 30, 2027, with potential full-time conversion subject to business needs and relocation requirements.
As a Senior ASIC & FPGA Design Engineer, you will lead and contribute to the design, verification, implementation, and integration of advanced hardware solutions. You will work across the engineering lifecycle to ensure designs meet functional, performance, quality, and reliability requirements.
ASIC and FPGA design: Design, develop, and implement digital ASICs, FPGAs, and potentially mixed-signal ASICs using hardware description languages such as VHDL, Verilog, and SystemVerilog.
RTL development and implementation: Translate design specifications and architectural requirements into efficient, synthesizable RTL, addressing performance, resource utilization, and implementation constraints.
Verification methodology: Develop verification strategies, test benches, and test harnesses for block-level and system-level designs to ensure functional correctness and design reliability.
Test planning and coverage: Create and execute comprehensive test plans, implement coverage models, and establish verification processes that identify design issues early in the development cycle.
Timing and design signoff: Conduct timing analysis, noise analysis, and other signoff checks to validate design integrity and compliance with technical specifications.
Design optimization and troubleshooting: Identify and resolve implementation challenges involving timing closure, congestion, and other hardware design constraints, driving issues through to resolution.
Cross-functional collaboration: Work closely with systems engineers, firmware developers, architects, and product engineering teams to align hardware designs with broader system requirements.
Laboratory integration and testing: Support hardware integration, lab testing, debugging, and troubleshooting activities to validate performance in practical operating environments.
Physical design support: Contribute to physical design and implementation flows, including RTL-to-GDSII processes and signoff activities, where applicable.
Continuous improvement and technical guidance: Apply industry best practices, explore design improvements, and share technical expertise with colleagues. Depending on project needs, provide mentorship to junior engineers.
We are looking for a highly experienced hardware design engineer with strong digital design fundamentals, hands-on ASIC and FPGA implementation experience, and the ability to solve complex technical challenges. The ideal candidate combines deep knowledge of hardware description languages and verification techniques with analytical thinking, effective communication, and the ability to collaborate across engineering disciplines.
Required qualifications and skills:
At least 7 years of experience in ASIC design and implementation.
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Practical experience with ASIC and FPGA design and development.
Proficiency in at least one major hardware description language: VHDL, Verilog, or SystemVerilog.
Experience working in a Linux-based development environment.
Hands-on experience developing verification methodologies, test benches, and test plans.
Understanding of digital design principles, implementation constraints, and functional verification processes.
Experience analyzing design performance and resolving implementation issues.
Strong problem-solving and analytical skills, with the ability to troubleshoot complex hardware design challenges.
Effective communication and collaboration skills to work with cross-functional engineering teams.
Ability to work independently, manage technical priorities, and deliver high-quality results in a remote engineering environment.
Preferred qualifications and experience:
Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
Experience across the full ASIC and FPGA lifecycle, including architecture, design, simulation, verification, validation, integration, and testing.
Familiarity with Software-Defined Radio (SDR) architectures, analog-to-digital and digital-to-analog converters (ADC/DAC), and digital signal processors (DSPs).
Knowledge of digital signal processing and communications systems, including spread spectrum, forward error correction, and modulation techniques such as QPSK, QAM, PCM/FM, and PAM.
Strong object-oriented programming and scripting skills using Python, Tcl, Perl, or similar languages.
Experience with physical design flows and industry-standard electronic design automation (EDA) tools.
Knowledge of RTL-to-GDSII implementation and physical design signoff processes.
Familiarity with deep-submicron FinFET and CMOS technologies.
Experience with design-for-test (DFT) methodologies, including scan, memory built-in self-test (MBIST), and logic built-in self-test (LBIST).
Previous experience mentoring junior engineers or providing technical leadership.
Strong stakeholder management skills and the ability to communicate complex technical concepts clearly.
Competitive hourly compensation: $100–$110 per hour on a W-2 employment basis, depending on qualifications and experience.
Fully remote contract: Work remotely throughout the initial contract period, subject to applicable employment requirements.
Defined contract duration: Initial engagement scheduled from October 12, 2026, through June 30, 2027.
Potential full-time conversion: Opportunity to transition to a full-time position, subject to business needs and successful conversion arrangements.
Relocation pathway for full-time conversion: If converted to a full-time position, relocation to one of the designated client locations in Southern California or Austin, Texas, will be required.
Professional growth: Gain experience working on complex ASIC and FPGA design challenges across hardware development and verification.
Multidisciplinary collaboration: Work with specialists across systems, firmware, architecture, and product engineering.
Benefits package: A comprehensive benefits package may be available subject to employment status and eligibility.
