The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.
Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.
EXP: 2-5 yrs or Equivalent or Relavent
Minimum Qualifications & Professional Experience:
• 2-5 years (with BTech) or 4 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 2-3 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.