Senior DSP SW Engineer

What you will do:

Independently own the design, implementation, and integration of a 5G NR physical-layer (PHY) subsystem for satellite non-terrestrial networks (NTN), translating system requirements into algorithms, firmware interfaces, and measurable acceptance criteria.
Define and execute PHY/link-level simulation studies for the subsystem, select representative NTN operating conditions and corner cases, and resolve tradeoffs among link performance, implementation complexity, latency, memory, and power.
Deliver and optimize production DSP firmware for the subsystem, including real-time processing, data movement, and accelerator interaction. Work with ASIC engineers to reduce power through efficient computation, memory access, and power-state control while meeting real-time deadlines; diagnose performance bottlenecks and integration failures.
Own the subsystem's reference models and ASIC test-vector deliverables, including fixed-point behavior, interface specifications, automated comparisons, and regression coverage agreed with design and verification teams.
Contribute to SystemC transaction-level modeling (TLM) and high-level synthesis (HLS) development, including synthesizable implementations, with guidance from engineers experienced in these flows.
Drive the subsystem's pre-silicon verification and new-chip bring-up activities, define tests and expected results, and resolve discrepancies across models, firmware, and hardware.
Review algorithms, code, and test plans; mentor less experienced engineers and coordinate technical dependencies with ASIC, verification, and software teams.

What you bring to this role:

Demonstrated ability to design and deliver communication DSP algorithms, explain their performance limits, and make implementation tradeoffs using simulation and measured results.
Ability to implement and debug numerical algorithms in C/C++, and to use Python or MATLAB for simulation, analysis, and test automation.
Practical experience implementing 5G NR PHY functions and interpreting the relevant 3GPP specifications, with the ability to turn requirements into subsystem designs and validation plans.
Demonstrated experience converting floating-point algorithms to fixed-point implementations, selecting numerical precision, and validating performance against a reference model.
Demonstrated ownership of real-time embedded DSP software, including profiling, optimization, hardware/software integration, and systematic debugging on an embedded target. Experience developing low-power firmware in collaboration with ASIC designers and evaluating power, performance, and memory tradeoffs.
Ability to build reproducible tests, use version control, document technical assumptions and results, and explain discrepancies during code and design reviews.
Evidence of independently delivering a PHY subsystem or comparable modem capability through integration and validation, and improving others' work through technical reviews or mentoring.
Typical background: BS with 7+ years, MS with 5+ years, or PhD with 3+ years of relevant experience in DSP, wireless communications, or embedded modem development, with a degree in Electrical Engineering, Computer Engineering, or a related field; equivalent demonstrated expertise is also welcome. These are guidelines, not mandatory minimums. Relevant doctoral research may count toward experience; demonstrated implementation and delivery capability remains essential.

Bonus points for the following:

Experience building SystemC TLM models for hardware/software integration or performance analysis, or delivering synthesizable HLS blocks with verified functional behavior and evaluated latency, throughput, and resource use.
Experience with 5G NR or NTN algorithms and specifications, satellite channel modeling, or compensation for Doppler and timing effects.
Experience taking modem functions through pre-silicon verification and silicon bring-up, including correlation of simulation results with hardware measurements.
Experience with 5G NR MAC, PHY/MAC interfaces, scheduling interactions, or HARQ procedures.
Experience implementing and optimizing algorithms on vector DSPs, including SIMD intrinsics, vectorization, and efficient memory access.
Experience validating ASIC power-management features through firmware, including clock or power gating, retention, and sleep/wake transitions under real-time constraints.

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.