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Sr Principal Design Engineer at cadence in 上海市 | Swiftcruit
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
Responsibilities:
Working in Cadence Flagship Emulation and Prototyping product line;
Responsible for designing, developing, modifying and productizing protocol products like PCIe, advanced Ethernet and many more which are crucial to modern IC design and verification.
Perform as individual contributor on protocol projects involving logic RTL design, UVM based verification, board design/debug and documentation etc.
Work on complex problems related to protocol or system integration level issues, electrical or timing closure issues, RTL design or verification methodologies.
Requirements:
The position requires MSEE or equivalent, with experience in logic design and debug.
Must have excellent communication skills, both written and verbal.
RTL design experience using Verilog is required along with experience in using RTL verification tools and flows.
Experience in FPGA design for Xilinx products is strongly recommended.
UVM verification experience is desired.
Experience with scripting languages like Perl, TCL C-shell is desired.
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