At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform…
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.
A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.
Key responsibilities:
- Define and implement SoC level DFT architecture for large and complex designs.
- Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
- Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
- Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
- Support post-silicon debug, failure analysis and yield learning.
- Collaborate with RTL, verification, physical design and operation teams.
Qualifications:
- BS with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum of 1 year of experience
- At least 3 years of hands-on experience in SoC DFT.
Must-have skills:
- Strong expertise in SCAN, ATPG, MBIST.
- Experience with pre-silicon validation and post-silicon debug.
- Strong problem solving and debugging skills.
- Ability to work effectively in a cross-functional engineering environment.
Good-to-have skills:
- Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
- Experience with IP-level DFT integration and reuse.
- Exposure to low-power DFT considerations and complex clocking architectures.
- Familiarity with manufacturing test flows and silicon yield improvement.
We’re doing work that matters. Help us solve what others can’t.
