Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Duties:

• Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
• Lead the verification effort for Cadence Memory Controller development.
• Contribute to the functional verification of Cadence's Memory Controller IP.
• Work with the existing functional verification environment to add new features into the verification environment.
• Ensure various customer configurations are clean as part of verification regressions.
• Support customers in case of any issues with using the verification environment and provide functional and code coverage.
• Ensure that the design is in line with the technical and quality requirements set for the team, particularly with respect to our quality metrics.
• Some telecommuting permitted. 

Qualifications:

• Bachelor’s degree in Electronic Engineering, Electrical Engineering, or related field.
• Minimum seven (7) years of progressive, post-baccalaureate experience in the job offered or in a related occupation.
• Design verification including writing detailed verification documents, test case development, and checking test results
• Functional verification fundamentals, environment planning, test plan generation, and environment development
• Universal Verification Methodology (UVM) based functional verification environment development
• System Verilog Assertions (SVA) for protocol checker development
• Debug failures and report issues found in design
• Functional coverage analysis and closure

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